Memory refresh - Revision history

Jnc: prepare for move

2022-09-20T00:15:10Z

prepare for move

Jnc: Jnc moved page Refresh to Memory refresh over a redirect without leaving a redirect: Put a dab here

2022-09-20T00:13:13Z

Jnc moved page Refresh to Memory refresh over a redirect without leaving a redirect: Put a dab here

Jnc: /* See also */ +Display refresh

2022-08-30T15:52:34Z

‎See also: +Display refresh

Jnc: +cat

2018-12-13T14:33:00Z

+cat

Jnc: Mention refresh in older tech

2018-10-07T18:01:09Z

Mention refresh in older tech

Jnc: A decent start

2018-06-18T15:54:14Z

A decent start

New page

'''Refresh''' is a fundamental part of the operation of [[Dynamic RAM]] [[memory]]. Since DRAM consists of an [[array ]]of small [[capacitor]]s (one for each 'cell', which can store one [[bit]]), which use the presence or absence of a stored charge in the capacitor to indicate the value of the bit stored in each cell, and over time that charge dissipates as the [[electron]]s slowly leak away, those cells holding a charge must periodically have it 'refreshed' on a regular basis, or the value of the bit will be lost.

To do this, the data in the cells is read out, and then re-written. This is not done with normal read and write operations, since that would take too long (below). Instead, refresh makes use of the fact that in a DRAM, the cells are in a square (normally) array; to do the refresh, an entire row or column is simultaneously read into a special array of [[latch]]es inside the DRAM [[integrated circuit]], and then written back from there. This avoids having to move the data in and out of the chip, which would inevitably be slower since there are many fewer signal paths in and out of the chip.

Generally one row or column is done at a time, with a pause before the next one is done; since the memory cannot respond to requests to read or write data while the refresh is happening, this minimizes the impact of any particular refresh cycle - although the total overhead of refresh (normally a few % of the overall time) is not changed by the use of the pauses.

The time between consecutive refresh operations to a given cell is typically in the low numbers of milliseconds.

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-'''Refresh''' is a fundamental part of the operation of all [[memory]] technologies which uses storage of groups of [[electron]]s to hold data. Over time that charge dissipates as the electrons slowly leak away, so they must periodically be 'refreshed' on a regular basis, or the data will be lost.
+'''Memory refresh''' is a fundamental part of the operation of all [[memory]] technologies which uses storage of groups of [[electron]]s to hold data. Over time that charge dissipates as the electrons slowly leak away, so they must periodically be 'refreshed' on a regular basis, or the data will be lost.
-Although historical technologies used in [[main memory]] such as the [[Williams tube]] had to deal with this, it is now mostly an issue with [[Dynamic RAM]] memory.
+Although historical technologies used in [[main memory]], such as the [[Williams tube]], had to deal with this, it is now mostly an issue with [[Dynamic RAM]] memory.
 DRAM consists of an [[array]] of small [[capacitor]]s (one for each 'cell', which can store one [[bit]]), which use the presence or absence of a stored charge in the capacitor to indicate the value of the bit stored in that cell. Those cells holding a charge must periodically be refreshed, or the values of those bits will be lost.

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 '''Refresh''' is a fundamental part of the operation of all [[memory]] technologies which uses storage of groups of [[electron]]s to hold data. Over time that charge dissipates as the electrons slowly leak away, so they must periodically be 'refreshed' on a regular basis, or the data will be lost.
-Although historical technologies used in [[main memory]] such as the [[Williams tube]] had to deal with this, it is now mostly an issue with [[Dynamic RAM]] memory. DRAM consists of an [[array]] of small [[capacitor]]s (one for each 'cell', which can store one [[bit]]), which use the presence or absence of a stored charge in the capacitor to indicate the value of the bit stored in that cell. Those cells holding a charge must periodically be refreshed, or the values of those bits will be lost.
+Although historical technologies used in [[main memory]] such as the [[Williams tube]] had to deal with this, it is now mostly an issue with [[Dynamic RAM]] memory.
-To do this, the data in the cells is read out, and then re-written. This is not done with normal read and write operations, since that would take too long (below). Instead, refresh makes use of the fact that in a DRAM, the cells are in a square (normally) array; to do the refresh, an entire row or column is simultaneously read into a special array of [[latch]]es inside the DRAM [[integrated circuit]], and then written back from there. This avoids having to move the data in and out of the chip, which would inevitably be slower since there are many fewer signal paths in and out of the chip.
+DRAM consists of an [[array]] of small [[capacitor]]s (one for each 'cell', which can store one [[bit]]), which use the presence or absence of a stored charge in the capacitor to indicate the value of the bit stored in that cell. Those cells holding a charge must periodically be refreshed, or the values of those bits will be lost.
 Generally one row or column is done at a time, with a pause before the next one is done; since the memory cannot respond to requests to read or write data while the refresh is happening, this minimizes the impact of any particular refresh cycle - although the total overhead of refresh (normally a few % of the overall time) is not changed by the use of the pauses.
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← Older revision	Revision as of 00:13, 20 September 2022
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