Micro-LINC 300 - Revision history

Jnc: /* External links */ +micro-LINC 300 in a museum

2026-09-07T15:14:30Z

External links: +micro-LINC 300 in a museum

← Older revision		Revision as of 15:14, 7 September 2026
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	* [https://archive.computerhistory.org/resources/access/text/2024/06/102785480-05-0001-acc.pdf SPEAR micro-LINC 300 Interim Data Sheet]		* [https://archive.computerhistory.org/resources/access/text/2024/06/102785480-05-0001-acc.pdf SPEAR micro-LINC 300 Interim Data Sheet]
			* [https://suomentietokonemuseo.fi/laitteet-esineet/#micro-linc-m1965 Finnish Computer Museum] - a micro-LINC 300 in a museum

	[[Category: Minicomputers]]		[[Category: Minicomputers]]
	[[Category: Personal Computers]]		[[Category: Personal Computers]]
	[[Category: 12-bit Computers]]		[[Category: 12-bit Computers]]

Jnc: /* External links */ +Interim Data Sheet, +cats

2026-09-07T15:06:12Z

External links: +Interim Data Sheet, +cats

← Older revision		Revision as of 15:06, 7 September 2026
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	The '''MSC 7''' instruction disables interrupts.		The '''MSC 7''' instruction disables interrupts.

			==External links==

			* [https://archive.computerhistory.org/resources/access/text/2024/06/102785480-05-0001-acc.pdf SPEAR micro-LINC 300 Interim Data Sheet]

			[[Category: Minicomputers]]
			[[Category: Personal Computers]]
			[[Category: 12-bit Computers]]

Larsbrinkhoff: /* Memory banks */ Fix wording.

2025-11-19T10:08:26Z

Memory banks: Fix wording.

← Older revision		Revision as of 10:08, 19 November 2025
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	===Memory banks===		===Memory banks===

	The [[primary memory]] can be up to 32K, divided into 32 1K pages. There are two five-bit registers, '''LP''' and '''UP'''. The '''LMB''' and '''UMB''' instructions set the lower and upper memory banks, i.e. LP or UP. Both instructions ~~take a five-bit page number. The~~ '''Z''' register ~~is set~~ an instruction code that will restore the previous bank, i.e. an LMB or UMB instruction with the previous page.		The [[primary memory]] can be up to 32K, divided into 32 1K "pages". There are two five-bit registers, '''LP''' and '''UP'''. The '''LMB''' and '''UMB''' instructions take a five-bit page number and set the lower and upper memory banks, i.e. LP or UP. Both instructions set the '''Z''' register to an instruction code that will restore the previous bank, i.e. an LMB or UMB instruction with the previous page.

	===Flag===		===Flag===

Larsbrinkhoff: More details.

2025-11-15T15:54:37Z

More details.

← Older revision		Revision as of 15:54, 15 November 2025
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	The '''micro-LINC 300''' was a [[LINC]] compatible computer by SPEaR, Inc. It came with 4K memory, expandable to 32K.		The '''micro-LINC 300''' was a [[LINC]] compatible computer by [[SPEaR, Inc]]. It was implemented with [[Motorola]] [[Emitter-coupled logic\|ECL]] parts and came with 4K memory, expandable to 32K.

	==Instruction set additions==		==Instruction set additions==

			This is mostly reverse engineered from schematics.

	===Memory banks===		===Memory banks===

	The [[primary memory]]] can be up to 32K, divided into 32 1K pages. There are two five-bit registers, '''LP''' and '''UP'''. The '''LMB''' and '''UMB''' instructions set the lower and upper memory banks, i.e. LP or UP. Both instructions take a five-bit page number. The '''Z''' register is set to the previous ~~contents of~~ the page ~~register~~.		The [[primary memory]] can be up to 32K, divided into 32 1K pages. There are two five-bit registers, '''LP''' and '''UP'''. The '''LMB''' and '''UMB''' instructions set the lower and upper memory banks, i.e. LP or UP. Both instructions take a five-bit page number. The '''Z''' register is set an instruction code that will restore the previous bank, i.e. an LMB or UMB instruction with the previous page.

	===Flag===		===Flag===
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	===Buffered tape===		===Buffered tape===

	Tape transfers can run in parallel with the processor. There is a new tape accumulator, '''TA'''. '''MSC 4''' transfers the TA to the regular accumulator. The '''MSC 3''' instruction makes a following tape instruction not pause. The '''SKP 16''' instruction skips if the tape is busy.		Tape transfers can run in parallel with the processor. There is a new tape accumulator, '''TA'''. '''MSC 4''' pauses if the tape is busy, and then transfers the TA to the regular accumulator. The '''MSC 3''' instruction makes a following tape instruction not pause. The '''SKP 16''' instruction skips if the tape is busy.

	===Disable interrupts===		===Disable interrupts===

	The '''MSC 7''' instruction disables interrupts.		The '''MSC 7''' instruction disables interrupts.

Larsbrinkhoff: Work in progress to reverse engineer the additions over a classic LINC.

2025-11-15T13:19:39Z

Work in progress to reverse engineer the additions over a classic LINC.

New page

The '''micro-LINC 300''' was a [[LINC]] compatible computer by SPEaR, Inc. It came with 4K memory, expandable to 32K.

==Instruction set additions==

===Memory banks===

The [[primary memory]]] can be up to 32K, divided into 32 1K pages. There are two five-bit registers, '''LP''' and '''UP'''. The '''LMB''' and '''UMB''' instructions set the lower and upper memory banks, i.e. LP or UP. Both instructions take a five-bit page number. The '''Z''' register is set to the previous contents of the page register.

===Flag===

There is an additional '''flag''' register, which is a single bit. The '''MSC 2''' instruction sets the flag, and the '''MSC 12''' clears it. '''SKP 17''' skips if the flag is set.

===Buffered tape===

Tape transfers can run in parallel with the processor. There is a new tape accumulator, '''TA'''. '''MSC 4''' transfers the TA to the regular accumulator. The '''MSC 3''' instruction makes a following tape instruction not pause. The '''SKP 16''' instruction skips if the tape is busy.

===Disable interrupts===

The '''MSC 7''' instruction disables interrupts.