Multi-port memory - Revision history

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2018-12-15T14:36:44Z

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2018-04-28T13:52:02Z

‎Implementation: ention use of arbiter

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A '''multi-port memory''' is a memory bank (usually of [[main memory]]) which can be physically connected to multiple clients (typically [[Central Processing Unit|CPUs]], [[Direct Memory Access|DMA]] [[device controller]]s, etc).

==Implementation==

The internal implementation can vary considerably; there are a number of approaches, based on cost, performance, etc goals.

The simplest choice is a priority arrangement, where the ports are numbered. and the memory controller attends to requests in priority order.

If there are multiple banks in the memory, then as long as access requests are spread out fairly evenly across them, it may be possible to perform memory cycles on separate ports simultaneously. (This approach was used on the [[PDP-10]] and [[Honeywell 6000 series|Honeywell 6000]] systems.)

For small multi-port memories, it is possible to replicate the memories, so no read contention ever happens (since each port has its own private copy of all the data). If more than one port can write, however, contention may arise in the writing.

The topic remains an area of research to the current day.

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−	A '''multi-port memory''' is a memory bank (usually of [[main memory]]) which can be physically separately connected to multiple clients (typically [[Central Processing Unit\|CPUs]], [[channel]]s. [[Direct Memory Access\|DMA]] [[device controller]]s, etc).	+	A '''multi-port memory''' is a memory bank (usually of [[main memory]]) which can be physically separately connected to multiple clients (typically [[Central Processing Unit\|CPUs]], [[channel]]s, [[Direct Memory Access\|DMA]] [[device controller]]s, etc).

	==Implementation==		==Implementation==

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−	A '''multi-port memory''' is a memory bank (usually of [[main memory]]) which can be physically separately connected to multiple clients (typically [[Central Processing Unit\|CPUs]], [[Direct Memory Access\|DMA]] [[device controller]]s, etc).	+	A '''multi-port memory''' is a memory bank (usually of [[main memory]]) which can be physically separately connected to multiple clients (typically [[Central Processing Unit\|CPUs]], [[channel]]s. [[Direct Memory Access\|DMA]] [[device controller]]s, etc).

	==Implementation==		==Implementation==

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	The topic remains an area of research to the current day.		The topic remains an area of research to the current day.

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-A '''multi-port memory''' is a memory bank (usually of [[main memory]]) which can be physically connected to multiple clients (typically [[Central Processing Unit|CPUs]], [[Direct Memory Access|DMA]] [[device controller]]s, etc).
+A '''multi-port memory''' is a memory bank (usually of [[main memory]]) which can be physically separately connected to multiple clients (typically [[Central Processing Unit|CPUs]], [[Direct Memory Access|DMA]] [[device controller]]s, etc).
 ==Implementation==
@@ Line 7: / Line 7: @@
 The simplest choice is a priority arrangement, where the ports are numbered. and the memory controller attends to requests in priority order, using an [[arbiter]] to deal with requests that arrive simultaneously.
-If there are multiple banks in the memory, then as long as access requests are spread out fairly evenly across them, it may be possible to perform memory cycles on separate ports simultaneously. (This approach was used on the [[PDP-10]] and [[Honeywell 6000 series|Honeywell 6000]] systems.)
+If there are multiple banks in the memory, then as long as access requests are spread out fairly evenly across them, it may be possible to perform memory cycles to different clients on separate ports simultaneously. (This approach was used on the [[PDP-10]] and [[Honeywell 6000 series|Honeywell 6000]] systems.)
 For small multi-port memories, it is possible to replicate the memories, so no read contention ever happens (since each port has its own private copy of all the data). If more than one port can write, however, contention may arise in the writing.

@@ Line 5: / Line 5: @@
 The internal implementation can vary considerably; there are a number of approaches, based on cost, performance, etc goals.
-The simplest choice is a priority arrangement, where the ports are numbered. and the memory controller attends to requests in priority order.
+The simplest choice is a priority arrangement, where the ports are numbered. and the memory controller attends to requests in priority order, using an [[arbiter]] to deal with requests that arrive simultaneously.
 If there are multiple banks in the memory, then as long as access requests are spread out fairly evenly across them, it may be possible to perform memory cycles on separate ports simultaneously. (This approach was used on the [[PDP-10]] and [[Honeywell 6000 series|Honeywell 6000]] systems.)