OMNIBUS - Revision history

Jnc: /* External links */ +OMNIBUS specification

2021-09-19T02:52:39Z

External links: +OMNIBUS specification

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	==External links==		==External links==

	* [https://homepage.divms.uiowa.edu/~jones/pdp8/hard8e/modules.html ~~Omnibus~~ Modules]		* [https://ethw.org/w/images/2/21/OMNI-spec.pdf OMNIBUS specification]
			* [https://homepage.divms.uiowa.edu/~jones/pdp8/hard8e/modules.html OMNIBUS Modules]

	[[Category: DEC Buses]]		[[Category: DEC Buses]]
	[[Category: OMNIBUS]]		[[Category: OMNIBUS]]

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2021-09-18T12:36:02Z

typo

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	==External links==		==External links==

	* [https://homepage.divms.uiowa.edu/~jones/pdp8/hard8e/modules.html Omnibus Modules		* [https://homepage.divms.uiowa.edu/~jones/pdp8/hard8e/modules.html Omnibus Modules]

	[[Category: DEC Buses]]		[[Category: DEC Buses]]
	[[Category: OMNIBUS]]		[[Category: OMNIBUS]]

Jnc: /* External links */ +Omnibus Modules

2021-09-18T12:34:05Z

External links: +Omnibus Modules

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	*[[:Category: OMNIBUS Peripherals‎\|OMNIBUS Peripherals]]		*[[:Category: OMNIBUS Peripherals‎\|OMNIBUS Peripherals]]

			==External links==

			* [https://homepage.divms.uiowa.edu/~jones/pdp8/hard8e/modules.html Omnibus Modules

	[[Category: DEC Buses]]		[[Category: DEC Buses]]
	[[Category: OMNIBUS]]		[[Category: OMNIBUS]]

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2021-05-14T00:45:10Z

Move 3CDB to separate page

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	The '''OMNIBUS''' was [[Digital Equipment Corporation\|DEC]]'s [[peripheral]] [[bus]] for the later [[PDP-8 family\|PDP-8]]'s; it was introduced with the [[PDP-8/E]], in 1970. It provided three kinds of cycles (as in earlier PDP-8's):		The '''OMNIBUS''' was [[Digital Equipment Corporation\|DEC]]'s [[peripheral]] [[bus]] for the later [[PDP-8 family\|PDP-8]]'s; it was introduced with the [[PDP-8/E]], in 1970. It provided three kinds of cycles (as in earlier PDP-8's):

	* ''Programmed data transfers'', in which the [[Central Processing Unit\|CPU]] reads or writes data to the [[device controller]];		* ''Programmed data transfers'', [[programmed I/O]], in which the [[Central Processing Unit\|CPU]] reads or writes data to the [[device controller]];
	* ''Program interrupt transfers''. in which the controller [[interrupt]]s the CPU;		* ''Program interrupt transfers'', in which the controller [[interrupt]]s the CPU;
	* '''''Data break transfers''''', the PDP-8 term for [[Direct Memory Access\|DMA]].		* '''''Data break transfers''''', the PDP-8 term for [[Direct Memory Access\|DMA]].

	In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory\|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.		In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory\|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.

	There were two different forms of the data break. In the first, the ''three cycle data break'', the word count and buffer address are stored in main memory~~, at~~ an ~~[[address]] supplied by the device (generally from hard-wired [[jumper]]s, as this mechanism was intended to economize on the [[hardware]] in the device). An~~ operation would include three memory cycles, one each to read and update the count and address, and one to actually do the operation. In the second, the ''single cycle data break'', the address was supplied by the device, which also kept track of the count, and only the actual data transfer occurred; this had less bus overhead, but required a more complex controller.		There were two different forms of the data break. In the first, the [[three cycle data break]], the word count and buffer address are stored in main memory; an operation would include three memory cycles, one each to read and update the count and address, and one to actually do the operation (hence the name). In the second, the ''single cycle data break'', the address was supplied by the device, which also kept track of the count, and only the actual data transfer occurred; this had less bus overhead, but required a more complex controller.

	The OMNIBUS was physically implemented as a large [[backplane]], into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots.		The OMNIBUS was physically implemented as a large [[backplane]], into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots.

Jnc: /* See also */ +1

2021-04-29T17:43:49Z

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2021-01-09T14:15:28Z

bold redir target

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	* ''Programmed data transfers'', in which the [[Central Processing Unit\|CPU]] reads or writes data to the [[device controller]];		* ''Programmed data transfers'', in which the [[Central Processing Unit\|CPU]] reads or writes data to the [[device controller]];
	* ''Program interrupt transfers''. in which the controller [[interrupt]]s the CPU;		* ''Program interrupt transfers''. in which the controller [[interrupt]]s the CPU;
	* ''Data break transfers'', the PDP-8 term for [[Direct Memory Access\|DMA]].		* '''''Data break transfers''''', the PDP-8 term for [[Direct Memory Access\|DMA]].

	In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory\|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.		In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory\|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.

Jnc: Proper cat

2018-10-20T02:15:49Z

Proper cat

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	In [[analog]] electrical terms, it was very similar to the [[UNIBUS]]; mostly bi-directional [[transmission line]]s, with a few uni-directional control lines. The [[terminator]]s and [[voltage]] levels of the two were the same, and they shared driver and receiver circuitry.		In [[analog]] electrical terms, it was very similar to the [[UNIBUS]]; mostly bi-directional [[transmission line]]s, with a few uni-directional control lines. The [[terminator]]s and [[voltage]] levels of the two were the same, and they shared driver and receiver circuitry.

			{{semi-stub}}

	[[Category: DEC Buses]]		[[Category: DEC Buses]]

	~~{{stub}}~~

Jnc: Fix error - same age

2018-09-05T03:29:49Z

Fix error - same age

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	In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory\|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.		In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory\|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.

	There were two different ~~versions (generations)~~ of the data break. In the first, the ''three cycle data break'', the word count and buffer address are stored in main memory, at an [[address]] supplied by the device (generally from hard-wired [[jumper]]s, as this mechanism was intended to economize on the [[hardware]] in the device). An operation would include three memory cycles, one each to read and update the count and address, and one to actually do the operation. In the ~~later~~ ''single cycle data break'', the address was supplied by the device, which also kept track of the count, and only the actual data transfer occurred; this had less bus overhead, but required more complex ~~controllers~~.		There were two different forms of the data break. In the first, the ''three cycle data break'', the word count and buffer address are stored in main memory, at an [[address]] supplied by the device (generally from hard-wired [[jumper]]s, as this mechanism was intended to economize on the [[hardware]] in the device). An operation would include three memory cycles, one each to read and update the count and address, and one to actually do the operation. In the second, the ''single cycle data break'', the address was supplied by the device, which also kept track of the count, and only the actual data transfer occurred; this had less bus overhead, but required a more complex controller.

	The OMNIBUS was physically implemented as a large [[backplane]], into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots.		The OMNIBUS was physically implemented as a large [[backplane]], into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots.

Jnc: +link, explanation

2018-09-04T17:03:34Z

+link, explanation

← Older revision		Revision as of 17:03, 4 September 2018
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	The '''OMNIBUS''' was [[Digital Equipment Corporation\|DEC]]'s [[bus]] for the later [[PDP-8 family\|PDP-8]]'s; it was introduced with the [[PDP-8/E]], in 1970. It provided three kinds of cycles (as in earlier PDP-8's):		The '''OMNIBUS''' was [[Digital Equipment Corporation\|DEC]]'s [[peripheral]] [[bus]] for the later [[PDP-8 family\|PDP-8]]'s; it was introduced with the [[PDP-8/E]], in 1970. It provided three kinds of cycles (as in earlier PDP-8's):

	* ''Programmed data transfers'', in which the [[Central Processing Unit\|CPU]] reads or writes data to the [[device controller]];		* ''Programmed data transfers'', in which the [[Central Processing Unit\|CPU]] reads or writes data to the [[device controller]];
Line 7:		Line 7:
	In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory\|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.		In addition to the usual read and write operations, a data break could also do an incremement operation, where a [[word]] was read out of [[main memory]] ([[core memory\|core]] at the time), incremented, and written back during the 'write back' phase of the core cycle.

	There were two different versions (generations) of the data break. In the first, the ''three cycle data break'', the word count and buffer address are stored in main memory, at an address supplied by the device (generally from hard-wired [[jumper]]s, as this mechanism was intended to economize on the [[hardware]] in the device). An operation would include three memory cycles, one each to read and update the count and address, and one to actually do the operation. In the ''single cycle data break'', the address was supplied by the device, which also kept track of the count, and only the actual data transfer occurred.		There were two different versions (generations) of the data break. In the first, the ''three cycle data break'', the word count and buffer address are stored in main memory, at an [[address]] supplied by the device (generally from hard-wired [[jumper]]s, as this mechanism was intended to economize on the [[hardware]] in the device). An operation would include three memory cycles, one each to read and update the count and address, and one to actually do the operation. In the later ''single cycle data break'', the address was supplied by the device, which also kept track of the count, and only the actual data transfer occurred; this had less bus overhead, but required more complex controllers.

	The OMNIBUS was physically implemented as a large [[backplane]], into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots.		The OMNIBUS was physically implemented as a large [[backplane]], into which were plugged both the CPU, and the device controllers; device controllers did not have dedicated slots.
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	[[Category: DEC Buses]]		[[Category: DEC Buses]]

			{{stub}}

Jnc: Typo

2018-09-04T12:43:52Z

Typo

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	The '''OMNIBUS''' was [[Digital Equipment Corporation\|DEC]]'s [[bus]] for the later [[PDP-8 family\|PDP-8]]'s; it was introduced with the [[PDP-8/E]], in 1970. It provided three kinds of cycles (as in earlier PDP-8's):		The '''OMNIBUS''' was [[Digital Equipment Corporation\|DEC]]'s [[bus]] for the later [[PDP-8 family\|PDP-8]]'s; it was introduced with the [[PDP-8/E]], in 1970. It provided three kinds of cycles (as in earlier PDP-8's):

← Older revision		Revision as of 17:43, 29 April 2021
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	{{semi-stub}}		{{semi-stub}}

			==See also==

			*[[:Category: OMNIBUS Peripherals‎\|OMNIBUS Peripherals]]

	[[Category: DEC Buses]]		[[Category: DEC Buses]]
			[[Category: OMNIBUS]]