PDP-10 memories - Revision history

Jnc: interleaving cleanup

2023-07-31T01:27:33Z

interleaving cleanup

Jnc: +link

2022-10-24T15:11:47Z

+link

Jnc: Move S/X details to mem bus page

2022-10-23T13:29:59Z

Move S/X details to mem bus page

Jnc: bah, already said that

2022-04-22T10:02:25Z

bah, already said that

Jnc: add compatibles units

2022-04-22T09:59:22Z

add compatibles units

Jnc: cat caps

2022-04-22T02:40:32Z

cat caps

Jnc: Avoid redir

2021-10-13T13:21:36Z

Avoid redir

Jnc: correct conn nm

2021-10-12T19:06:02Z

correct conn nm

Jnc: +img KI-type mem bus QickConn latch

2021-10-12T17:57:26Z

+img KI-type mem bus QickConn latch

Jnc: update mem bus desc

2021-04-20T18:19:56Z

update mem bus desc

← Older revision		Revision as of 01:27, 31 July 2023
Line 1:		Line 1:
−	'''PDP-10 memories''' were generally all [[multi-port memory]] units. The [[PDP-10]] [[Central Processing Unit\|CPU]] used one port (one per CPU in [[multi-processor]] systems); the others are used by [[channel]]s for [[mass storage]], such as [[disk]]s, to do [[Direct Memory Access\|DMA]]. [[Interleaving]] was generally supported between units; usually in pairs, or sometimes groups of four. All except the very last ones were [[core memory\|core]], and supported [[parity]] for [[error detection]]; the others were [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]], and used [[Error-correcting code\|ECC]] to protect the memory contents.	+	'''PDP-10 memories''' were generally all [[multi-port memory]] units. The [[PDP-10]] [[Central Processing Unit\|CPU]] used one port (one per CPU in [[multi-processor]] systems); the others are used by [[channel]]s for [[mass storage]], such as [[disk]]s, to do [[Direct Memory Access\|DMA]]. [[Memory interleaving\|Interleaving]] was generally supported between units; usually in pairs, or sometimes groups of four. All except the very last ones were [[core memory\|core]], and supported [[parity]] for [[error detection]]; the others were [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]], and used [[Error-correcting code\|ECC]] to protect the memory contents.

	[[Image:KBusQCUnlatched.jpg\|250px\|thumb\|left\|KI-type memory bus Quick Latch connector (in unlatched position)]]		[[Image:KBusQCUnlatched.jpg\|250px\|thumb\|left\|KI-type memory bus Quick Latch connector (in unlatched position)]]

@@ Line 3: / Line 3: @@
 [[Image:KBusQCUnlatched.jpg|250px|thumb|left|KI-type memory bus Quick Latch connector (in unlatched position)]]
-There were three generations of [[main memory]] [[bus]] (which ran sequentially through memory units to a [[terminator]]), and memory units for them. The first two were the so-called 'external memory bus', in KA (18-bit [[address]]) and KI (22-bit) forms (for the [[KA10]], and [[KI10]] and early [[KL10]], respectively), although they also had [[protocol]] differences. The last was the 'internal memory bus', the 'S-Bus'. (For the later KL10s, a later version of the S-Bus, the X-Bus, differed only in the [[logic family]] it interfaced to.)
+There were three generations of [[main memory]] [[bus]] (which ran sequentially through memory units to a [[terminator]]), and memory units for them. The first two were the so-called 'external memory bus', in KA (18-bit [[address]]) and KI (22-bit) forms (for the [[KA10]], and [[KI10]] and early [[KL10]], respectively), although they also had [[protocol]] differences. The last was the 'internal memory bus', the [[PDP-10 Memory Bus|S-Bus]]. (For the later KL10s, a later version of the S-Bus, the X-Bus, differed only in the [[logic family]] it interfaced to.)
 The differences between the two external bus types required a [[KI10-M Memory Bus Adapter]] if KA-bit units were to be attached to a KI10. Similarly, KI-type units could be attached to the S-Bus using a [[DMA20 Memory Bus Adapter]].

@@ Line 3: / Line 3: @@
 [[Image:KBusQCUnlatched.jpg|250px|thumb|left|KI-type memory bus Quick Latch connector (in unlatched position)]]
-There were three generations of [[main memory]] [[bus]] (which ran sequentially through memory units to a [[terminator]]), and memory units for them. The first two were the so-called 'external memory bus', in KA (18-bit [[address]]) and KI (22-bit) forms (for the [[KA10]], and [[KI10]] and early [[KL10]], respectively), although they also had [[protocol]] differences. The last was the 'internal memory bus', the 'S-Bus'. (For the later KL10s, a later version of the S-Bus, the X-Bus, differed only in the [[logic family]] it interfaced to.) The  differences between the two external bus types required a [[KI10-M Memory Bus Adapter]] if KA-bit units were to be attached to a KI10. Similarly, KI-type units could be attached to the S-Bus using a [[DMA20 Memory Bus Adapter]].
+There were three generations of [[main memory]] [[bus]] (which ran sequentially through memory units to a [[terminator]]), and memory units for them. The first two were the so-called 'external memory bus', in KA (18-bit [[address]]) and KI (22-bit) forms (for the [[KA10]], and [[KI10]] and early [[KL10]], respectively), although they also had [[protocol]] differences. The last was the 'internal memory bus', the 'S-Bus'. (For the later KL10s, a later version of the S-Bus, the X-Bus, differed only in the [[logic family]] it interfaced to.)
-The S-Bus (and the later version, the X-Bus, used with MOS 'internal' memory) performs memory transfers in blocks of up to four [[word]]s, so that four words can be read in any cycle; the block can start with any word within the block. The KL10 contains a pair of S-Busses, designated 0 and 1.
+The differences between the two external bus types required a [[KI10-M Memory Bus Adapter]] if KA-bit units were to be attached to a KI10. Similarly, KI-type units could be attached to the S-Bus using a [[DMA20 Memory Bus Adapter]].
 Most the memory units had a configuration panel which allowed ports to be enabled, and set the memory's address (often independently for each port); similarly, some level of interleaving could be set.
@@ Line 46: / Line 46: @@
 The first two groups are all multi-port (generally 4 ports per memory system in the first group, and 8 in the second). The last group were for the later final KL10s (models KL10-E and KL10-R); all the DEC ones except the MF20 and MG20 were core.
 [[Category: PDP-10 Memories]]

@@ Line 1: / Line 1: @@
-'''PDP-10 memories''' were generally all [[multi-port memory]] units. The [[PDP-10]] [[Central Processing Unit|CPU]] used one port (one per CPU in [[multi-processor]] systems); the others are used by [[channel]]s for [[mass storage]], such as [[disk]]s. [[Interleaving]] was generally supported between units; usually in pairs, or sometimes groups of four. All except the very last ones were [[core memory|core]], and supported [[parity]] for [[error detection]]; the others were [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]], and used [[Error-correcting code|ECC]] to protect the memory contents.
+'''PDP-10 memories''' were generally all [[multi-port memory]] units. The [[PDP-10]] [[Central Processing Unit|CPU]] used one port (one per CPU in [[multi-processor]] systems); the others are used by [[channel]]s for [[mass storage]], such as [[disk]]s, to do [[Direct Memory Access|DMA]]. [[Interleaving]] was generally supported between units; usually in pairs, or sometimes groups of four. All except the very last ones were [[core memory|core]], and supported [[parity]] for [[error detection]]; the others were [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]], and used [[Error-correcting code|ECC]] to protect the memory contents.
 [[Image:KBusQCUnlatched.jpg|250px|thumb|left|KI-type memory bus Quick Latch connector (in unlatched position)]]
-There were three generations of [[main memory]] [[bus]] (which ran sequentially through memory units to a [[terminator]]), and memory units to them. The first two were the so-called 'external memory bus', in KA (18-bit [[address]]) and KI (22-bit) forms (for the [[KA10]], and [[KI10]] and early [[KL10]], respectively), although they also had [[protocol]] differences. The last was the 'internal memory bus', the 'S-Bus'. (For the later KL10s, a later version of the S-Bus, the X-Bus, differed only in the [[logic family]] it interfaced to.) The  differences between the two external bus types required a [[KI10-M Memory Bus Adapter]] if KA-bit units were to be attached to a KI10. Similarly, KI-type units could be attached to the S-Bus using a [[DMA20 Memory Bus Adapter]].
+There were three generations of [[main memory]] [[bus]] (which ran sequentially through memory units to a [[terminator]]), and memory units for them. The first two were the so-called 'external memory bus', in KA (18-bit [[address]]) and KI (22-bit) forms (for the [[KA10]], and [[KI10]] and early [[KL10]], respectively), although they also had [[protocol]] differences. The last was the 'internal memory bus', the 'S-Bus'. (For the later KL10s, a later version of the S-Bus, the X-Bus, differed only in the [[logic family]] it interfaced to.) The  differences between the two external bus types required a [[KI10-M Memory Bus Adapter]] if KA-bit units were to be attached to a KI10. Similarly, KI-type units could be attached to the S-Bus using a [[DMA20 Memory Bus Adapter]].
 The S-Bus (and the later version, the X-Bus, used with MOS 'internal' memory) performs memory transfers in blocks of up to four [[word]]s, so that four words can be read in any cycle; the block can start with any word within the block. The KL10 contains a pair of S-Busses, designated 0 and 1.
@@ Line 45: / Line 45: @@
 * [[Ampex ARM20]]
-The first two groups are all multi-port (necessary to allow [[mass storage]] on [[channel]]s to do [[Direct Memory Access|DMA]]; generally 4 ports per memory system in the first group, and 8 in the second). The last group were for the later final KL10s (models KL10-E and KL10-R); all the DEC ones except the MF20 and MG20 were core.
+The first two groups are all multi-port (generally 4 ports per memory system in the first group, and 8 in the second). The last group were for the later final KL10s (models KL10-E and KL10-R); all the DEC ones except the MF20 and MG20 were core.
 [[Category: PDP-10 Memories]]

@@ Line 8: / Line 8: @@
 Most the memory units had a configuration panel which allowed ports to be enabled, and set the memory's address (often independently for each port); similarly, some level of interleaving could be set.
 ==Memory systems==
--bit external:
+-bit external (DEC):
 * [[MA10 core memory|MA10]]
@@ Line 17: / Line 19: @@
 * [[MD10 core memory|MD10]]
--bit external:
+-bit external (others):
 * [[ME10 core memory|ME10]]
@@ Line 24: / Line 30: @@
 * [[MH10 core memory|MH10]]
-Internal:
+-bit external (others):
 * [[MA20 core memory|MA20]]
@@ Line 31: / Line 41: @@
 * [[MG20 MOS memory|MG20]]
-The first two groups are all multi-port (generally 4 ports per memory system in the first group, and 8 in the second). The last group were for the later final KL10s (models KL10-E and KL10-R). All except the MF20 and MG20 were core.
+Internal (others):
 [[Category: PDP-10 Memories]]

← Older revision		Revision as of 02:40, 22 April 2022
Line 33:		Line 33:
	The first two groups are all multi-port (generally 4 ports per memory system in the first group, and 8 in the second). The last group were for the later final KL10s (models KL10-E and KL10-R). All except the MF20 and MG20 were core.		The first two groups are all multi-port (generally 4 ports per memory system in the first group, and 8 in the second). The last group were for the later final KL10s (models KL10-E and KL10-R). All except the MF20 and MG20 were core.

−	[[Category: PDP-10 ~~memories~~]]	+	[[Category: PDP-10 Memories]]

@@ Line 1: / Line 1: @@
-'''PDP-10 memories''' were generally all [[multi-port memory]] units. The [[PDP-10]] [[Central Processing Unit|CPU]] used one port (one per CPU in [[multi-processor]] systems); the others are used by [[channel]]s for [[mass storage]], such as [[disk]]s. [[Interleaving]] was generally supported between units; usually in pairs, or sometimes groups of four. All the early ones were [[core memory|core]], and supported [[parity]] for [[error detection]]; later ones were [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]], and used [[Error-correcting code|ECC]] to protect the memory contents.
+'''PDP-10 memories''' were generally all [[multi-port memory]] units. The [[PDP-10]] [[Central Processing Unit|CPU]] used one port (one per CPU in [[multi-processor]] systems); the others are used by [[channel]]s for [[mass storage]], such as [[disk]]s. [[Interleaving]] was generally supported between units; usually in pairs, or sometimes groups of four. All except the very last ones were [[core memory|core]], and supported [[parity]] for [[error detection]]; the others were [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]], and used [[Error-correcting code|ECC]] to protect the memory contents.
-There were three generations of [[main memory]] [[bus]] (which ran sequentially through memory units to a [[terminator]]), and memory units to them. The first two were the so-called 'external memory bus', in KA (18-bit [[address]]) and KI (22-bit) forms (for the KA10, and KI10 and early KL10, respectively), although they also had [[protocol]] differences. The last was the 'internal memory bus', the 'S-Bus' (for the later KL10s, a later version of the S-Bus, the X-Bus, differed only in the [[logic family]] it interfaced to). The  differences between the two external bus types required a [[KI10-M Memory Bus Adapter]] if KA-bit units were to be attached to a KI10. Similarly, KI-type units could be attached to the S-Bus using a [[DMA20 Memory Bus Controller]].
+[[Image:KBusQCUnlatched.jpg|250px|thumb|left|KI-type memory bus Quick Connect latch (in unlatched position)]]
-The S-Bus (and a later version, the X-Bus, used with MOS 'internal' memory) performs memory transfers in blocks of up to four [[word]]s, so that four words can be read in any cycle; the block can start with any word within the block. The KL10 contains a pair of S-Busses, designated 0 and 1.
+There were three generations of [[main memory]] [[bus]] (which ran sequentially through memory units to a [[terminator]]), and memory units to them. The first two were the so-called 'external memory bus', in KA (18-bit [[address]]) and KI (22-bit) forms (for the [[KA10]], and [[KI10]] and early [[KL10]], respectively), although they also had [[protocol]] differences. The last was the 'internal memory bus', the 'S-Bus'. (For the later KL10s, a later version of the S-Bus, the X-Bus, differed only in the [[logic family]] it interfaced to.) The  differences between the two external bus types required a [[KI10-M Memory Bus Adapter]] if KA-bit units were to be attached to a KI10. Similarly, KI-type units could be attached to the S-Bus using a [[DMA20 Memory Bus Controller]].
 Most the memory units had a configuration panel which allowed ports to be enabled, and set the memory's address (often independently for each port); similarly, some level of interleaving could be set.