PDP-11/45 - Revision history

Jnc: /* External links */ +pdp11/45 processor handbook

2024-02-29T21:52:41Z

‎External links: +pdp11/45 processor handbook

Jnc: Move image into infobox

2024-02-08T17:10:59Z

Move image into infobox

Jnc: /* External links */ +11/55 FMPS

2022-03-06T21:08:52Z

‎External links: +11/55 FMPS

Jnc: /* External links */ +Eng drwngs, manuals

2022-02-24T19:34:35Z

‎External links: +Eng drwngs, manuals

Jnc: Avoid dab

2019-09-17T13:11:27Z

Avoid dab

Jnc: /* High-speed memory */ Mention RH11 config

2018-07-27T22:46:54Z

‎High-speed memory: Mention RH11 config

Jnc: /* High-speed memory */ More info

2018-07-27T19:13:14Z

‎High-speed memory: More info

Jnc: clearer

2018-05-20T15:01:42Z

clearer

Jnc: grammar

2018-05-20T14:57:40Z

grammar

Jnc: Refer to MS11 for new page on it

2018-05-20T11:32:01Z

Refer to MS11 for new page on it

@@ Line 64: / Line 64: @@
 * [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]
 * [http://www.bitsavers.org/pdf/dec/pdp11/1155/MP00039_1155vol1_Mar76.pdf 11/55 Vol. 1 Field Maintenance Print Set] (MP00039)
 {{Nav PDP-11}}
 [[Category: UNIBUS PDP-11s]]

@@ Line 1: / Line 1: @@
 {{Infobox Machine
-<!-- | image = PDP11-45.jpg
+| image = PDP11-45.jpg
-| caption = A PDP-11/45 Error? -->
+| imgwidth = 200px
 | name = PDP-11/45
 | manufacturer = [[Digital Equipment Corporation|DEC]]
@@ Line 15: / Line 14: @@
 | year introduced = June 1972
 |}}
 The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic.
@@ Line 49: / Line 47: @@
 == Gallery ==
 [[Image:PDP11-55-geerol.jpg|150px|A PDP-11/55 setup]]
 [[Image:PDP11-55-geerol2.jpg|150px|Different view of the PDP-11/55 setup]]

@@ Line 64: / Line 64: @@
 * [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun74.pdf PDP-11/45 system engineering drawings (June 1974)]
 * [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]
-{{PDP-11}}
+{{Nav PDP-11}}
 [[Category: UNIBUS PDP-11s]]

@@ Line 47: / Line 47: @@
 The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the [[PDP-11/70]], where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.
 </i>
 == Gallery ==
@@ Line 59: / Line 55: @@
 [[Image:pdp11-45.jpeg|150px|The "mysterious" PDP-11/45]]
 [[Image:labor114.jpg|150px|11/45 at the Technical University of Budapest: in the foreground you can see a Videoton VDT52100 (VT52-compatible) terminal.]]
 {{PDP-11}}
 [[Category: UNIBUS PDP-11s]]

@@ Line 18: / Line 18: @@
 The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic.
-The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor|FP11-B]] or [[FP11-C Floating-Point Processor|FP11-C]] [[Floating point processor|FPP]]. The [[FP11 Floating-Point Processor]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).
+The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor|FP11-B]] or [[FP11-C Floating-Point Processor|FP11-C]] [[Floating point processor|FPP]]. The [[FP11 floating point]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).
 The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor|MOS]] or 300 nsec [[bipolar]] memory, respectively.

@@ Line 26: / Line 26: @@
 ==High-speed memory==
-The MS11 high-speed memory was [[multi-port memory|dual-ported]]: one port went to a special high-speed [[bus]] to the CPU (called the Fastbus), which was part of the CPU's [[backplane]]; the other went to a second UNIBUS (the 'B' UNIBUS).
+The MS11 high-speed memory was [[multi-port memory|dual-ported]]: one port went to a special high-speed [[bus]] to the CPU (called the Fastbus), which was implemented as part of the CPU's [[backplane]]; the other went to a second UNIBUS (the 'B' UNIBUS).
-That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that [[Direct Memory Access|DMA]] devices on that UNIBUS could do [[input/output|I/O]] to that memory.
+That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that [[Direct Memory Access|DMA]] devices on that UNIBUS could do [[input/output|I/O]] to the fast memory, which was accessible only from the CPU when the two UNIBUSes were split.
-The high-speed memory could be configured in two semi-independent banks, each with its own M8110 (later M8120) Semiconductor Memory Control module.
+Note that if the system contained a dual-UNIBUS [[RH11 MASSBUS controller]], devices attached to that could reach the fast memory in a split-UNIBUS system if the RH11's second UNIBUS was attached to the 'B' UNIBUS, giving them a high-speed path to the memory on which there was no contention with the CPU.
-When the -11/45's CPU went to do a memory cycle, it started cycles on both the FastBus and the UNIBUS A; if that [[address]] was in an MS11, the MS11'scontroller indicated that it had it, over a special FastBus line. The UNIBUS cycle would then be abandoned before the CPU asserted MSYN.
+The high-speed memory could be configured in two semi-independent banks, each with its own dual-ported M8110 (later M8120) Semiconductor Memory Control module.
 A number of products from [[Able Computer]] made use of the FastBus; the [[Able CACHE/45]] (which provided a [[cache]]), and the [[Able SCAT/45]] (which was an MS11 equivalent which could support up to 256 Kbytes of memory).

@@ Line 20: / Line 20: @@
 The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor|FP11-B]] or [[FP11-C Floating-Point Processor|FP11-C]] [[Floating point processor|FPP]]. The [[FP11 Floating-Point Processor]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).
-The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with special high-speed [[Metal Oxide Semiconductor|MOS]] or [[bipolar]] [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), respectively.
+The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor|MOS]] or 300 nsec [[bipolar]] memory, respectively.
 The machine's 18-bit-address UNIBUS allowed it to have up to 256Kbytes of [[main memory]]. Later non-DEC products such as the [[Able ENABLE]] allowed use of up to 4Mbytes, via an [[Extended UNIBUS]].
@@ Line 26: / Line 26: @@
 ==High-speed memory==
-The high-speed memory was [[multi-port memory|dual-ported]], to a special high-speed [[bus]] to the CPU (called the Fastbus), which was part of the CPU's [[backplane]], and also to a second UNIBUS.
+The high-speed memory was [[multi-port memory|dual-ported]], to a special high-speed [[bus]] to the CPU (called the Fastbus), which was part of the CPU's [[backplane]], and also to a second UNIBUS (the 'B' UNIBUS).
 That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS, so that [[Direct Memory Access|DMA]] devices on that UNIBUS could do [[input/output|I/O]] to that memory.