PDP-11/45 - Revision history

Jnc: Fix minor error; Bitsavers file rename

2026-10-08T12:06:08Z

Fix minor error; Bitsavers file rename

← Older revision		Revision as of 12:06, 8 October 2026
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	The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor\|FP11-B]] or [[FP11-C Floating-Point Processor\|FP11-C]] [[Floating point processor\|FPP]]. The [[FP11 floating point]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).		The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor\|FP11-B]] or [[FP11-C Floating-Point Processor\|FP11-C]] [[Floating point processor\|FPP]]. The [[FP11 floating point]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).

	The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor\|MOS]] or 300 nsec [[bipolar]] memory, respectively.		The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor\|MOS]], or 300 nsec [[bipolar]] memory, respectively.

	The machine's 18-bit-address UNIBUS allowed it to have up to ~~256Kbytes~~ of [[main memory]]. Later non-DEC products such as the [[Able ENABLE]] allowed use of up to 4Mbytes, via an [[Extended UNIBUS]].		The machine's 18-bit-address UNIBUS allowed it to have up to 248Kbytes of [[main memory]]. Later non-DEC products such as the [[Able ENABLE]] allowed use of up to 4Mbytes, via an [[Extended UNIBUS]].

	==High-speed memory==		==High-speed memory==
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	* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]		* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]
	* [http://www.bitsavers.org/pdf/dec/pdp11/1155/MP00039_1155vol1_Mar76.pdf 11/55 Vol. 1 Field Maintenance Print Set] (MP00039)		* [http://www.bitsavers.org/pdf/dec/pdp11/1155/MP00039_1155vol1_Mar76.pdf 11/55 Vol. 1 Field Maintenance Print Set] (MP00039)
	* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/~~PDP1145_Handbook_1973~~.pdf pdp11/45 processor handbook]		* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP-1145_Handbook_1973.pdf pdp11/45 processor handbook]

	{{Nav PDP-11}}		{{Nav PDP-11}}

	[[Category: UNIBUS PDP-11s]]		[[Category: UNIBUS PDP-11s]]

Jnc: /* External links */ +pdp11/45 processor handbook

2024-02-29T21:52:41Z

External links: +pdp11/45 processor handbook

← Older revision		Revision as of 21:52, 29 February 2024
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	* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]		* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]
	* [http://www.bitsavers.org/pdf/dec/pdp11/1155/MP00039_1155vol1_Mar76.pdf 11/55 Vol. 1 Field Maintenance Print Set] (MP00039)		* [http://www.bitsavers.org/pdf/dec/pdp11/1155/MP00039_1155vol1_Mar76.pdf 11/55 Vol. 1 Field Maintenance Print Set] (MP00039)
			* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP1145_Handbook_1973.pdf pdp11/45 processor handbook]

	{{Nav PDP-11}}		{{Nav PDP-11}}

	[[Category: UNIBUS PDP-11s]]		[[Category: UNIBUS PDP-11s]]

Jnc: Move image into infobox

2024-02-08T17:10:59Z

Move image into infobox

← Older revision		Revision as of 17:10, 8 February 2024
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	~~[[Image:PDP11-45.jpg\|150px\|right\|thumb\|A PDP-11/45]]~~

	{{Infobox Machine		{{Infobox Machine
	~~<!--~~ \| image = PDP11-45.jpg		\| image = PDP11-45.jpg
	\| caption = A PDP-11/45 ~~Error? -->~~		\| imgwidth = 200px
			\| caption = A PDP-11/45
	\| name = PDP-11/45		\| name = PDP-11/45
	\| manufacturer = [[Digital Equipment Corporation\|DEC]]		\| manufacturer = [[Digital Equipment Corporation\|DEC]]
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	\| year introduced = June 1972		\| year introduced = June 1972
	\|}}		\|}}

	The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit\|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic.		The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit\|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic.

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	== Gallery ==		== Gallery ==

	[[Image:PDP11-55-geerol.jpg\|150px\|A PDP-11/55 setup]]		[[Image:PDP11-55-geerol.jpg\|150px\|A PDP-11/55 setup]]
	[[Image:PDP11-55-geerol2.jpg\|150px\|Different view of the PDP-11/55 setup]]		[[Image:PDP11-55-geerol2.jpg\|150px\|Different view of the PDP-11/55 setup]]

Jnc: /* External links */ +11/55 FMPS

2022-03-06T21:08:52Z

External links: +11/55 FMPS

← Older revision		Revision as of 21:08, 6 March 2022
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	* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun74.pdf PDP-11/45 system engineering drawings (June 1974)]		* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun74.pdf PDP-11/45 system engineering drawings (June 1974)]
	* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]		* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]
			* [http://www.bitsavers.org/pdf/dec/pdp11/1155/MP00039_1155vol1_Mar76.pdf 11/55 Vol. 1 Field Maintenance Print Set] (MP00039)

	{{PDP-11}}		{{Nav PDP-11}}

	[[Category: UNIBUS PDP-11s]]		[[Category: UNIBUS PDP-11s]]

Jnc: /* External links */ +Eng drwngs, manuals

2022-02-24T19:34:35Z

External links: +Eng drwngs, manuals

← Older revision		Revision as of 19:34, 24 February 2022
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	The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the [[PDP-11/70]], where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.		The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the [[PDP-11/70]], where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.
	</i>		</i>

	~~== Documentation ==~~

	* [http://toresbe.dreamhosters.com/redirect.php?res=bitsavers&doc=dec/pdp11/1145/EK-KB11A-MM-004_Aug76.pdf EK-KB11A-MM-xxx KB11-A Central Processor Unit Maintenance Manual]

	== Gallery ==		== Gallery ==
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	[[Image:pdp11-45.jpeg\|150px\|The "mysterious" PDP-11/45]]		[[Image:pdp11-45.jpeg\|150px\|The "mysterious" PDP-11/45]]
	[[Image:labor114.jpg\|150px\|11/45 at the Technical University of Budapest: in the foreground you can see a Videoton VDT52100 (VT52-compatible) terminal.]]		[[Image:labor114.jpg\|150px\|11/45 at the Technical University of Budapest: in the foreground you can see a Videoton VDT52100 (VT52-compatible) terminal.]]

			==External links==

			* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_SystemMan.pdf PDP-11/45, 11/50 and 11/55 system user's manual] (EK-1145-OP-001)
			* [http://www.bitsavers.org/pdf/dec/pdp11/1145/DEC-11-HMRMA-A-D_PDP-11_45_Maintenance_Reference_Manual_Nov72.pdf PDP-11/45 maintenance reference manual] (DEC-11-HMRMA-A-D)
			* [http://www.bitsavers.org/pdf/dec/pdp11/1145/EK-11045-MM-007.pdf PDP-11/45, 11/50 and 11/55 system maintenance manual] (EK-11045-MM-007)
			* [http://www.bitsavers.org/pdf/dec/pdp11/1145/PDP-11_45_and_70_Maintenance_Course_Handout_Book_1978.pdf PDP-11/45 /70 Maintenance Course handout book]
			* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun74.pdf PDP-11/45 system engineering drawings (June 1974)]
			* [http://www.bitsavers.org/pdf/dec/pdp11/1145/1145_System_Engineering_Drawings_Jun76.pdf PDP-11/45 system engineering drawings (June 1976)]

	{{PDP-11}}		{{PDP-11}}

	[[Category: UNIBUS PDP-11s]]		[[Category: UNIBUS PDP-11s]]

Jnc: Avoid dab

2019-09-17T13:11:27Z

Avoid dab

← Older revision		Revision as of 13:11, 17 September 2019
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	The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit\|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic.		The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit\|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic.

	The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor\|FP11-B]] or [[FP11-C Floating-Point Processor\|FP11-C]] [[Floating point processor\|FPP]]. The [[FP11 ~~Floating-Point Processor~~]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).		The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor\|FP11-B]] or [[FP11-C Floating-Point Processor\|FP11-C]] [[Floating point processor\|FPP]]. The [[FP11 floating point]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).

	The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor\|MOS]] or 300 nsec [[bipolar]] memory, respectively.		The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor\|MOS]] or 300 nsec [[bipolar]] memory, respectively.

Jnc: /* High-speed memory */ Mention RH11 config

2018-07-27T22:46:54Z

High-speed memory: Mention RH11 config

← Older revision		Revision as of 22:46, 27 July 2018
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	==High-speed memory==		==High-speed memory==

	The MS11 high-speed memory was [[multi-port memory\|dual-ported]]: one port went to a special high-speed [[bus]] to the CPU (called the Fastbus), which was part of the CPU's [[backplane]]; the other went to a second UNIBUS (the 'B' UNIBUS).		The MS11 high-speed memory was [[multi-port memory\|dual-ported]]: one port went to a special high-speed [[bus]] to the CPU (called the Fastbus), which was implemented as part of the CPU's [[backplane]]; the other went to a second UNIBUS (the 'B' UNIBUS).

	That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that [[Direct Memory Access\|DMA]] devices on that UNIBUS could do [[input/output\|I/O]] to ~~that~~ memory.		That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that [[Direct Memory Access\|DMA]] devices on that UNIBUS could do [[input/output\|I/O]] to the fast memory, which was accessible only from the CPU when the two UNIBUSes were split.

	~~The high~~-~~speed~~ memory ~~could be configured~~ in ~~two semi~~-~~independent banks~~, ~~each~~ with ~~its own M8110 (later M8120) Semiconductor Memory Control module~~.		Note that if the system contained a dual-UNIBUS [[RH11 MASSBUS controller]], devices attached to that could reach the fast memory in a split-UNIBUS system if the RH11's second UNIBUS was attached to the 'B' UNIBUS, giving them a high-speed path to the memory on which there was no contention with the CPU.

	When the -11/45's CPU went to do a memory cycle, it started cycles on both the FastBus and the UNIBUS A; if that [[address]] was in an MS11, the MS11'~~scontroller~~ indicated that it had it, over a special FastBus line. The UNIBUS cycle would then be abandoned before the CPU asserted MSYN.		The high-speed memory could be configured in two semi-independent banks, each with its own dual-ported M8110 (later M8120) Semiconductor Memory Control module.

			When the -11/45's CPU went to do a memory cycle, it started cycles on both the FastBus and the 'A' UNIBUS; if that [[address]] was in an MS11, the MS11's controller indicated that it had it, over a special FastBus line. The UNIBUS cycle would then be abandoned before the CPU asserted MSYN.

	A number of products from [[Able Computer]] made use of the FastBus; the [[Able CACHE/45]] (which provided a [[cache]]), and the [[Able SCAT/45]] (which was an MS11 equivalent which could support up to 256 Kbytes of memory).		A number of products from [[Able Computer]] made use of the FastBus; the [[Able CACHE/45]] (which provided a [[cache]]), and the [[Able SCAT/45]] (which was an MS11 equivalent which could support up to 256 Kbytes of memory).

Jnc: /* High-speed memory */ More info

2018-07-27T19:13:14Z

High-speed memory: More info

← Older revision		Revision as of 19:13, 27 July 2018
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	==High-speed memory==		==High-speed memory==

	The high-speed memory was [[multi-port memory\|dual-ported]], to a special high-speed [[bus]] to the CPU (called the Fastbus), which was part of the CPU's [[backplane]]~~, and also~~ to a second UNIBUS (the 'B' UNIBUS).		The MS11 high-speed memory was [[multi-port memory\|dual-ported]]: one port went to a special high-speed [[bus]] to the CPU (called the Fastbus), which was part of the CPU's [[backplane]]; the other went to a second UNIBUS (the 'B' UNIBUS).

	That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS, so that [[Direct Memory Access\|DMA]] devices on that UNIBUS could do [[input/output\|I/O]] to that memory.		That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that [[Direct Memory Access\|DMA]] devices on that UNIBUS could do [[input/output\|I/O]] to that memory.

	The high-speed memory could be configured in two semi-independent banks, each with its own M8110 (later M8120) Semiconductor Memory Control module.		The high-speed memory could be configured in two semi-independent banks, each with its own M8110 (later M8120) Semiconductor Memory Control module.

			When the -11/45's CPU went to do a memory cycle, it started cycles on both the FastBus and the UNIBUS A; if that [[address]] was in an MS11, the MS11'scontroller indicated that it had it, over a special FastBus line. The UNIBUS cycle would then be abandoned before the CPU asserted MSYN.

			A number of products from [[Able Computer]] made use of the FastBus; the [[Able CACHE/45]] (which provided a [[cache]]), and the [[Able SCAT/45]] (which was an MS11 equivalent which could support up to 256 Kbytes of memory).

	== hampage.hu ==		== hampage.hu ==

Jnc: clearer

2018-05-20T15:01:42Z

clearer

← Older revision		Revision as of 15:01, 20 May 2018
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	The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor\|FP11-B]] or [[FP11-C Floating-Point Processor\|FP11-C]] [[Floating point processor\|FPP]]. The [[FP11 Floating-Point Processor]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).		The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor\|FP11-B]] or [[FP11-C Floating-Point Processor\|FP11-C]] [[Floating point processor\|FPP]]. The [[FP11 Floating-Point Processor]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).

	The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with special high-speed ~~[[Metal Oxide Semiconductor\|MOS]] or [[bipolar]]~~ [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), respectively.		The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor\|MOS]] or 300 nsec [[bipolar]] memory, respectively.

	The machine's 18-bit-address UNIBUS allowed it to have up to 256Kbytes of [[main memory]]. Later non-DEC products such as the [[Able ENABLE]] allowed use of up to 4Mbytes, via an [[Extended UNIBUS]].		The machine's 18-bit-address UNIBUS allowed it to have up to 256Kbytes of [[main memory]]. Later non-DEC products such as the [[Able ENABLE]] allowed use of up to 4Mbytes, via an [[Extended UNIBUS]].
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	==High-speed memory==		==High-speed memory==

	The high-speed memory was [[multi-port memory\|dual-ported]], to a special high-speed [[bus]] to the CPU (called the Fastbus), which was part of the CPU's [[backplane]], and also to a second UNIBUS.		The high-speed memory was [[multi-port memory\|dual-ported]], to a special high-speed [[bus]] to the CPU (called the Fastbus), which was part of the CPU's [[backplane]], and also to a second UNIBUS (the 'B' UNIBUS).

	That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS, so that [[Direct Memory Access\|DMA]] devices on that UNIBUS could do [[input/output\|I/O]] to that memory.		That UNIBUS could either be connected to a second PDP-11 (creating a [[multi-processor]] PDP-11 system), or the -11/45's main UNIBUS, so that [[Direct Memory Access\|DMA]] devices on that UNIBUS could do [[input/output\|I/O]] to that memory.

Jnc: grammar

2018-05-20T14:57:40Z

grammar

← Older revision		Revision as of 14:57, 20 May 2018
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	The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with special high-speed [[Metal Oxide Semiconductor\|MOS]] or [[bipolar]] [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), respectively.		The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with special high-speed [[Metal Oxide Semiconductor\|MOS]] or [[bipolar]] [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), respectively.

	The machine's 18-bit UNIBUS~~, allowing~~ it to have up to 256Kbytes of [[main memory]]. Later non-DEC products such as the [[Able ENABLE]] allowed use of up to 4Mbytes, via ~~the~~ [[Extended UNIBUS]].		The machine's 18-bit-address UNIBUS allowed it to have up to 256Kbytes of [[main memory]]. Later non-DEC products such as the [[Able ENABLE]] allowed use of up to 4Mbytes, via an [[Extended UNIBUS]].

	==High-speed memory==		==High-speed memory==

← Older revision		Revision as of 13:11, 17 September 2019
Line 18:		Line 18:
	The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit\|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic.		The '''PDP-11/45''' was the early fast [[UNIBUS]] [[PDP-11]] system, using the [[KB11-A CPU]] (early units, prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit\|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic.

	The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor\|FP11-B]] or [[FP11-C Floating-Point Processor\|FP11-C]] [[Floating point processor\|FPP]]. The [[FP11 ~~Floating-Point Processor~~]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).		The difference between the two CPUs was whether they worked with the [[FP11-B Floating-Point Processor\|FP11-B]] or [[FP11-C Floating-Point Processor\|FP11-C]] [[Floating point processor\|FPP]]. The [[FP11 floating point]] was optional, as was the [[KT11-C Memory Management Unit]] (the first implementation of the full [[PDP-11 Memory Management]]).

	The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor\|MOS]] or 300 nsec [[bipolar]] memory, respectively.		The '''PDP-11/50''' and '''PDP-11/55''' were systems which used the exact same processor, but were sold pre-configured with the special high-speed [[MS11 Semiconductor Memory System]] (specific to the PDP-11/45), using 350 nsec [[Metal Oxide Semiconductor\|MOS]] or 300 nsec [[bipolar]] memory, respectively.