PDP-11/74 - Revision history

Vaxorcist: Corrected picture naming

2024-12-22T15:13:03Z

Corrected picture naming

Vaxorcist at 15:10, 22 December 2024

2024-12-22T15:10:29Z

Jnc: typo

2021-08-21T20:57:21Z

typo

Jnc: +good ext page; update cause of cancellation

2021-08-21T16:25:03Z

+good ext page; update cause of cancellation

Jnc: +cat

2018-12-19T23:38:06Z

+cat

Jnc: Proper cat

2018-10-20T16:13:03Z

Proper cat

Jnc: +link

2018-08-20T10:55:14Z

+link

Jnc: An OK start

2018-08-19T19:09:24Z

An OK start

New page

The '''PDP-11/74''' was a tightly-coupled symmetric [[multi-processor]] version of the [[PDP-11/70]]; it could hold from two to four [[Central Processing Unit|CPUs]].

It used a [[multi-port memory]] version of the [[MK11 memory system]], the MKA11. Some [[peripheral|devices]], such as [[disk]]s and [[magnetic tape drive]]s, could be shared between two of the CPUs, using the multi-port capabilities of many [[MASSBUS]] devices; other devices (e.g. [[UNIBUS]] devices) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]).

The CPU was the [[KB11-E CPU]], a modified version of the [[KB11-C CPU]] of the -11/70. An Interprocessor Interrupt (IIST) facility in each CPU, interconnected over a private [[bus]], allowed one CPU to interrupt or [[bootstrap]] another CPU. A multi-ported high-resolution 'Time of Day' [[clock]] was also provided. Also, the ASRB instruction was modified to be [[atomic]], for synchronization between CPUs.

There was also a planned [[Commercial Instruction Set]] processor, the CISP.

A significant run of prototypes were produced, and the [[RSX-11]] [[operating system]] was enhanced to support multi-processor operation. The -11/74 was cancelled, however (reputedly because of concern that with its very high [[input/output|I/O]] bandwidth, it would compete with the new [[VAX-11/780]]), and never appeared as a product.

{{stub}}

{{PDP-11}}

@@ Line 1: / Line 1: @@
 The '''PDP-11/74''' was an experimental (it never went into production) tightly-coupled symmetric [[multi-processor]] version of the [[PDP-11/70]] from [[Digital Equipment Corporation|DEC]]; it could hold from two to four [[Central Processing Unit|CPUs]].
-[[File:PDP-11-74.jpg|thumb|left|alt=A cartoon centipede reads books and types on a laptop.|The Wikipede edits ''[[Myriapoda]]''.]]
+[[File:PDP-11-74.jpg|thumb|left|The PDP-11/74]]
 It used a [[multi-port memory]] version of the [[MK11 memory system]], the MKA11. Some [[peripheral|devices]], such as [[disk]]s and [[magnetic tape drive]]s, could be shared between two of the CPUs, using the multi-port capabilities of many [[MASSBUS]] devices; other devices (e.g. [[UNIBUS]] devices) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]).

← Older revision		Revision as of 15:10, 22 December 2024
Line 1:		Line 1:
	The '''PDP-11/74''' was an experimental (it never went into production) tightly-coupled symmetric [[multi-processor]] version of the [[PDP-11/70]] from [[Digital Equipment Corporation\|DEC]]; it could hold from two to four [[Central Processing Unit\|CPUs]].		The '''PDP-11/74''' was an experimental (it never went into production) tightly-coupled symmetric [[multi-processor]] version of the [[PDP-11/70]] from [[Digital Equipment Corporation\|DEC]]; it could hold from two to four [[Central Processing Unit\|CPUs]].
		+
		+	[[File:PDP-11-74.jpg\|thumb\|left\|alt=A cartoon centipede reads books and types on a laptop.\|The Wikipede edits ''[[Myriapoda]]''.]]

	It used a [[multi-port memory]] version of the [[MK11 memory system]], the MKA11. Some [[peripheral\|devices]], such as [[disk]]s and [[magnetic tape drive]]s, could be shared between two of the CPUs, using the multi-port capabilities of many [[MASSBUS]] devices; other devices (e.g. [[UNIBUS]] devices) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]).		It used a [[multi-port memory]] version of the [[MK11 memory system]], the MKA11. Some [[peripheral\|devices]], such as [[disk]]s and [[magnetic tape drive]]s, could be shared between two of the CPUs, using the multi-port capabilities of many [[MASSBUS]] devices; other devices (e.g. [[UNIBUS]] devices) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]).

@@ Line 7: / Line 7: @@
 There was also a planned [[Commercial Instruction Set]] processor, the CISP.
-A significant run of prototypes were produced, and the [[RSX-11]] [[operating system]] was enhanced to support multi-processor operation. The -11/74 was cancelled, however (reputedly the concern as that with its very high [[input/output|I/O]] bandwidth, it would compete with the new [[VAX-11/780]], but this appears to be a canard; concern about its commercial viability was apparently the cause), and never appeared as a product.
+A significant run of prototypes were produced, and the [[RSX-11]] [[operating system]] was enhanced to support multi-processor operation. The -11/74 was cancelled, however (reputedly the concern was that with its very high [[input/output|I/O]] bandwidth, it would compete with the new [[VAX-11/780]], but this appears to be a canard; concern about its commercial viability was apparently the cause), and never appeared as a product.
 {{semi-stub}}

@@ Line 1: / Line 1: @@
-The '''PDP-11/74''' was a tightly-coupled symmetric [[multi-processor]] version of the [[PDP-11/70]]; it could hold from two to four [[Central Processing Unit|CPUs]].
+The '''PDP-11/74''' was an experimental (it never went into production) tightly-coupled symmetric [[multi-processor]] version of the [[PDP-11/70]] from [[Digital Equipment Corporation|DEC]]; it could hold from two to four [[Central Processing Unit|CPUs]].
 It used a [[multi-port memory]] version of the [[MK11 memory system]], the MKA11. Some [[peripheral|devices]], such as [[disk]]s and [[magnetic tape drive]]s, could be shared between two of the CPUs, using the multi-port capabilities of many [[MASSBUS]] devices; other devices (e.g. [[UNIBUS]] devices) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]).
@@ Line 7: / Line 7: @@
 There was also a planned [[Commercial Instruction Set]] processor, the CISP.
-A significant run of prototypes were produced, and the [[RSX-11]] [[operating system]] was enhanced to support multi-processor operation. The -11/74 was cancelled, however (reputedly because of concern that with its very high [[input/output|I/O]] bandwidth, it would compete with the new [[VAX-11/780]]), and never appeared as a product.
+A significant run of prototypes were produced, and the [[RSX-11]] [[operating system]] was enhanced to support multi-processor operation. The -11/74 was cancelled, however (reputedly the concern as that with its very high [[input/output|I/O]] bandwidth, it would compete with the new [[VAX-11/780]], but this appears to be a canard; concern about its commercial viability was apparently the cause), and never appeared as a product.
 {{semi-stub}}
 {{PDP-11}}
 [[Category: UNIBUS PDP-11s]]

← Older revision		Revision as of 23:38, 19 December 2018
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	{{PDP-11}}		{{PDP-11}}
		+
		+	[[Category: UNIBUS PDP-11s]]

@@ Line 3: / Line 3: @@
 It used a [[multi-port memory]] version of the [[MK11 memory system]], the MKA11. Some [[peripheral|devices]], such as [[disk]]s and [[magnetic tape drive]]s, could be shared between two of the CPUs, using the multi-port capabilities of many [[MASSBUS]] devices; other devices (e.g. [[UNIBUS]] devices) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]).
-The CPU was the [[KB11-E CPU]], a modified version of the [[KB11-C CPU]] of the -11/70. An Interprocessor Interrupt (IIST) facility in each CPU, interconnected over a private [[bus]], allowed one CPU to interrupt or [[bootstrap]] another CPU. A multi-ported high-resolution 'Time of Day' [[clock]] was also provided. Also, the ASRB instruction was modified to be [[atomic]], for synchronization between CPUs.
+The CPU was the [[KB11-E CPU]], a modified version of the [[KB11-C CPU]] of the -11/70. An Interprocessor Interrupt (IIST) facility in each CPU, interconnected over a private [[bus]], allowed one CPU to [[interrupt]] or [[bootstrap]] another CPU. A multi-ported high-resolution 'Time of Day' [[clock]] was also provided. Also, the ASRB instruction implementation was modified to be [[atomic]], for use in synchronization between CPUs.
 There was also a planned [[Commercial Instruction Set]] processor, the CISP.