PDP-11/84 - Revision history

Jnc: Missed another /83 image

2024-10-10T12:35:36Z

Missed another /83 image

Jnc: /* Gallery */ Move -11/83 image

2024-10-10T12:31:26Z

‎Gallery: Move -11/83 image

Jnc: Link KDJ11 PMI/UNIBUS backplane

2024-10-08T11:33:46Z

Link KDJ11 PMI/UNIBUS backplane

Jnc: /* External links */ +PDP-11 Systems Handbook

2024-02-29T21:23:07Z

‎External links: +PDP-11 Systems Handbook

Jnc: /* External links */ +Preliminary PDP-11/84 System Technical and Reference Manual

2024-02-06T15:18:50Z

‎External links: +Preliminary PDP-11/84 System Technical and Reference Manual

Jnc: /* External links */ +FMPS, manuals

2022-02-19T11:33:40Z

‎External links: +FMPS, manuals

Jnc: +backplane number

2021-03-12T15:48:22Z

+backplane number

Jnc: Move backplane details to KTJ11-B page (the /94 has the same backplane)

2020-01-29T22:02:00Z

Move backplane details to KTJ11-B page (the /94 has the same backplane)

Jnc: /* QBUS slots */ Update for potential CPU issues

2018-07-26T14:25:23Z

‎QBUS slots: Update for potential CPU issues

Jnc: clarify

2018-07-05T16:50:55Z

clarify

@@ Line 1: / Line 1: @@
 The '''PDP-11/84''' is the [[UNIBUS]]-capable twin to the [[QBUS]]-only [[PDP-11/83]]; both used the [[KDJ11-B CPU]] (with its [[Private Memory Interconnect|PMI]] bus). The -11/84 added a [[KTJ11-B UNIBUS adapter]] to provide its UNIBUS, and required a custom main [[backplane]], the [[KDJ11 PMI/UNIBUS backplane]], to support it.
 == hampage.hu ==
-[[Image:mpdp11-83.jpg|left|thumb|200px|PDP-11/84]]
 Quoting:
 <i>
@@ Line 9: / Line 11: @@
 The UNIBUS-based PDP-11/84 was for those customers, who wanted more I/O throughput or had some legacy equipment.
-The box on the picture to the left is a BA123 which was a popular enclosure for QBUS machines. Apart from the 12x4-slot QBUS backplane, it had five slots for storage units, e.g. room for two or three harddisks, a tape drive ([[TK50]] here) and floppy.
+The box used was the BA123 which was a popular enclosure for QBUS machines. Apart from the 12x4-slot QBUS backplane, it had five slots for storage units, e.g. room for two or three hard disks, a tape drive ([[TK50]] here) and floppy.
 </i>
+<!--
 <br clear=all>
 == Gallery ==
+-->
 ==External links==

@@ Line 11: / Line 11: @@
 The box on the picture to the left is a BA123 which was a popular enclosure for QBUS machines. Apart from the 12x4-slot QBUS backplane, it had five slots for storage units, e.g. room for two or three harddisks, a tape drive ([[TK50]] here) and floppy.
 </i>
 == Gallery ==
 [[Image:PDP11-84.JPG|200px|A PDP-11/84]]

← Older revision		Revision as of 11:33, 8 October 2024
Line 1:		Line 1:
−	The '''PDP-11/84''' is the [[UNIBUS]]-capable twin to the [[QBUS]]-only [[PDP-11/83]]; both used the [[KDJ11-B CPU]] (with its [[Private Memory Interconnect\|PMI]] bus). The -11/84 added a [[KTJ11-B UNIBUS adapter]] to provide its UNIBUS, and ~~had~~ a custom main [[backplane]] ~~(H9277-A~~, [[~~DEC part number~~]] ~~70-20650-01)~~ to ~~[[KTJ11-B UNIBUS adapter#Backplane details\|~~support]] it.	+	The '''PDP-11/84''' is the [[UNIBUS]]-capable twin to the [[QBUS]]-only [[PDP-11/83]]; both used the [[KDJ11-B CPU]] (with its [[Private Memory Interconnect\|PMI]] bus). The -11/84 added a [[KTJ11-B UNIBUS adapter]] to provide its UNIBUS, and required a custom main [[backplane]], the [[KDJ11 PMI/UNIBUS backplane]], to support it.

	== hampage.hu ==		== hampage.hu ==

@@ Line 23: / Line 23: @@
 * [http://www.bitsavers.org/pdf/dec/pdp11/1184/EK-1184A-MG-001_1184maint_Nov86.pdf PDP-11/84 System Maintenance Guide] (EK-1184A-MG-001)
 * [http://www.bitsavers.org/pdf/dec/pdp11/1184/MP-02015-01_11-84_Maintenance_Print_Set_198412.pdf 11/84 Field Maintenance Print Set] (MP-02015-01)
 {{PDP-11}}
 [[Category: UNIBUS PDP-11s]]

@@ Line 19: / Line 19: @@
 ==External links==
 * [http://www.bitsavers.org/pdf/dec/pdp11/1184/EK-1184E-TM-001_Dec87.pdf PDP-11/84 System Technical and Reference Manual] (EK-1184E-TM-001)
 * [http://www.bitsavers.org/pdf/dec/pdp11/1184/EK-1184A-MG-001_1184maint_Nov86.pdf PDP-11/84 System Maintenance Guide] (EK-1184A-MG-001)
@@ Line 25: / Line 26: @@
 {{PDP-11}}
-[[Category:UNIBUS PDP-11s]]
+[[Category: UNIBUS PDP-11s]]

← Older revision		Revision as of 15:48, 12 March 2021
Line 1:		Line 1:
−	The '''PDP-11/84''' is the [[UNIBUS]]-capable twin to the [[QBUS]]-only [[PDP-11/83]]; both used the [[KDJ11-B CPU]] (with its [[Private Memory Interconnect\|PMI]] bus). The -11/84 added a [[KTJ11-B UNIBUS adapter]] to provide its UNIBUS, and had a custom main [[backplane]] to [[KTJ11-B UNIBUS adapter#Backplane details\|support]] it.	+	The '''PDP-11/84''' is the [[UNIBUS]]-capable twin to the [[QBUS]]-only [[PDP-11/83]]; both used the [[KDJ11-B CPU]] (with its [[Private Memory Interconnect\|PMI]] bus). The -11/84 added a [[KTJ11-B UNIBUS adapter]] to provide its UNIBUS, and had a custom main [[backplane]] (H9277-A, [[DEC part number]] 70-20650-01) to [[KTJ11-B UNIBUS adapter#Backplane details\|support]] it.

	== hampage.hu ==		== hampage.hu ==

← Older revision		Revision as of 22:02, 29 January 2020
Line 1:		Line 1:
−	The '''PDP-11/84''' is the [[UNIBUS]]-capable twin to the [[QBUS]]-only [[PDP-11/83]]; both used the [[KDJ11-B CPU]] (with its [[Private Memory Interconnect\|PMI]] bus). The -11/84 added a [[KTJ11-B UNIBUS adapter]] to provide its UNIBUS, and had a main [[backplane]] ~~which was half QBUS, and half UNIBUS, with a slot in the middle for the~~ KTJ11-B.	+	The '''PDP-11/84''' is the [[UNIBUS]]-capable twin to the [[QBUS]]-only [[PDP-11/83]]; both used the [[KDJ11-B CPU]] (with its [[Private Memory Interconnect\|PMI]] bus). The -11/84 added a [[KTJ11-B UNIBUS adapter]] to provide its UNIBUS, and had a custom main [[backplane]] to [[KTJ11-B UNIBUS adapter#Backplane details\|support]] it.
−
−	The backplane contains (in order) four [[DEC card form factor\|quad-height]] slots, the first of which is a custom slot, and the others are PMI (technically [[QBUS#Variable address size\|Q22]]/[[CD interconnect\|CD]], although slightly modified from the normal form of that in this backplane, see below); they are used for (in order, from the front of the machine):
−
−	* the Machine Debug Monitor board (M7677); this slot is not numbered
−	* the [[Central Processing Unit\|CPU]] board; this is slot 1
−	* [[main memory]] board
−	* optional second main memory board
−
−	~~and nine hex-height slots, used for:~~
−
−	* UNIBUS ~~adaptor, in slot 4~~
−	* four [[Small Peripheral Controller\|SPC]] UNIBUS slots
−	* three [[Modified UNIBUS Device\|MUD]] UNIBUS slots
−	* UNIBUS 'out' and quad SPC slot, in slot 12
−
−	~~Note that the PMI slots do not have the [[CD interconnect~~#~~Use by PMI\|bottom-up]] ordering of PMI-capable slots in a Q22/CD backplane, but are wired as a true bus, allowing the 'CPU, memory, memory' insertion ordering seen here.~~
−
−	~~Note also that in the normal configuration (see below for~~ details~~), the QBUS [[bus grant line]]s are not routed through the memory slots, so if one of these slot is unused, there is no need for a [[jumper]] card in that slot.~~
−
−	As a further feature, on most UNIBUS backplanes, the 'NPG' ([[Direct Memory Access\|DMA]] grant line) signal is carried across unused slots by wire jumpers on [[wire-wrap]] pins on the back side of the backplane; on the -11/84 backplane, they are brought out to a [[Dual Inline Package\|~~DIP~~]] ~~switch on the MDM module, for easier configuration changes.~~
−
−	~~==QBUS slots==~~
−
−	The two main memory slots can in fact be configured as regular Q22/CD QBUS slots, by removing two jumpers. EK-PDP84-TM-PR4 (PDP-11/84 Technical Manual) says (in section 2.1.14, "Backplane (H9277-A)", pg. 2-6):
−
−	~~: ''Bus signals BDMGI (pin AR2) and BIAKI (pin AM2) for slots 2 & 3 are jumpered on the front of the backplane.''~~
−
−	There are indeed two jumpers, W1 and W2 (in the upper right-hand corner, when facing the backplane from the board insertion side); the traces connected to them are on the surface, so it is possible to see where they go: one end runs to a trace connected from slot 1 to slot 2, and the other to a trace connected from slot 3 to slot 4; those connect to AM2 (BIAKI) and AN2 (BIAKO), and AR2 (BDMGI) and AS2 (BDMGO).
−
−	Thus, when the jumpers are in, the CPU's BIAKO/BDMGO pins are connected directly to the UNIBUS adapter's BIAKI/BDMGI pins; when they are out, those signals are routed through the two 'memory' slots, in the normal QBUS manner.
−
−	It therefore seems those two slots ''might'' be able to function as real QBUS slots. However, it is not clear that the CPU will 'do the right thing'; the UNIBUS adapter puts out a signal to let the CPU know that it is there, and the CPU may then expect to see only PMI-type DMA and interrupt cycles on the bus.
−
−	~~The DMA cycle ''might'' work,~~ it all depends on what happens at step 8 (EK-KDJ1B-UG-001, pp. 7-6 to 7-9) when, instead of PBSY being asserted, BSYNC is asserted. The ''memory'' will be fine (since in an -11/83, this kind of thing is expected)... but the ''CPU'', who knows.
−
−	[[Interrupt]] cycles are more problematic; the assertion of the interrupt level on the BDAL lines (step 1a) will probably pass, but step 6 (assertion of BSACK) may be an issue, since the device will want to assert BRPLY instead (BSACK is not used in a QBUS interrupt), and the CPU may not do the right thing.

	== hampage.hu ==		== hampage.hu ==

@@ Line 31: / Line 31: @@
 Thus, when the jumpers are in, the CPU's BIAKO/BDMGO pins are connected directly to the UNIBUS adapter's BIAKI/BDMGI pins; when they are out, those signals are routed through the two 'memory' slots, in the normal QBUS manner.
-It therefore seems those two slots ''can'' function as real QBUS slots. (If not, why arrange things so that the  can run grant lines through them?) As far as is known, this has not yet been verified, though.
+It therefore seems those two slots ''might'' be able to function as real QBUS slots. However, it is not clear that the CPU will 'do the right thing'; the UNIBUS adapter puts out a signal to let the CPU know that it is there, and the CPU may then expect to see only PMI-type DMA and interrupt cycles on the bus.
-As to why DEC put this capability in, and then didn't more widely document it, or use it: that is not known. Perhaps they thought it would introduce extra complixity in the user instructions, or something?
+The DMA cycle ''might'' work, it all depends on what happens at step 8 (EK-KDJ1B-UG-001, pp. 7-6 to 7-9) when, instead of PBSY being asserted, BSYNC is asserted. The ''memory'' will be fine (since in an -11/83, this kind of thing is expected)... but the ''CPU'', who knows.
 == hampage.hu ==

@@ Line 11: / Line 11: @@
 * UNIBUS adaptor, in slot 4
-* four [[Small Peripheral Controller|SPC]] slots
+* four [[Small Peripheral Controller|SPC]] UNIBUS slots
-* three [[Modified UNIBUS Device|MUD]] slots
+* three [[Modified UNIBUS Device|MUD]] UNIBUS slots
 * UNIBUS 'out' and quad SPC slot, in slot 12
-Note that the PMI slots do not have the [[CD interconnect#Use by PMI|bottom-up]] ordering of PMI-capable slots in a Q22/CD backplane, but are wired as a true bus, allowing the 'CPU, memory, memory' insertion ordering.
+Note that the PMI slots do not have the [[CD interconnect#Use by PMI|bottom-up]] ordering of PMI-capable slots in a Q22/CD backplane, but are wired as a true bus, allowing the 'CPU, memory, memory' insertion ordering seen here.
-Note also that in the normal configuration (see below for details), the QBUS [[bus grant line]]s are not routed through the memory slots, so if a slot is unused, there is no need for a [[jumper]] card in that slot.
+Note also that in the normal configuration (see below for details), the QBUS [[bus grant line]]s are not routed through the memory slots, so if one of these slot is unused, there is no need for a [[jumper]] card in that slot.
-On most UNIBUS backplanes, the 'NPG' ([[Direct Memory Access|DMA]] grant line) signal is carried across unused slots by wire jumpers on the [[wire-wrap]] pins on the back side of the backplane; on the -11/84 backplane, they are brought out to a [[Dual Inline Package|DIP]] switch on the MDM module.
+As a further feature, on most UNIBUS backplanes, the 'NPG' ([[Direct Memory Access|DMA]] grant line) signal is carried across unused slots by wire jumpers on [[wire-wrap]] pins on the back side of the backplane; on the -11/84 backplane, they are brought out to a [[Dual Inline Package|DIP]] switch on the MDM module, for easier configuration changes.
 ==QBUS slots==
@@ Line 29: / Line 29: @@
 There are indeed two jumpers, W1 and W2 (in the upper right-hand corner, when facing the backplane from the board insertion side); the traces connected to them are on the surface, so it is possible to see where they go: one end runs to a trace connected from slot 1 to slot 2, and the other to a trace connected from slot 3 to slot 4; those connect to AM2 (BIAKI) and AN2 (BIAKO), and AR2 (BDMGI) and AS2 (BDMGO).
-Thus, when the jumpers are in, the CPU's BIAKO/BDMGO pins are connected directly to the UNIBUS adapter's BIAKI/BDMGI pins; when they are out, those signals are routed through the two 'memory' slots, in the normal QBUS manner. It therefore seems those two slots ''can'' function as real QBUS slots. (If not, why arrange things so that the  can run grant lines through them?) As far as is known, this has not yet been verified, though.
+Thus, when the jumpers are in, the CPU's BIAKO/BDMGO pins are connected directly to the UNIBUS adapter's BIAKI/BDMGI pins; when they are out, those signals are routed through the two 'memory' slots, in the normal QBUS manner.
-As to why DEC put this capability in, and then didn't more widely document it, or use it: that is not known. Perhaps they thought it would introduce extra complixity in the user instructions, or something.
+It therefore seems those two slots ''can'' function as real QBUS slots. (If not, why arrange things so that the  can run grant lines through them?) As far as is known, this has not yet been verified, though.
 == hampage.hu ==