PDP-11 Memory Management - Revision history

Jnc: /* Further reading */ +Extended Memory for the LSI-11

2024-07-27T17:20:00Z

‎Further reading: +Extended Memory for the LSI-11

Jnc: rm bloat

2023-07-02T16:10:35Z

rm bloat

Jnc: /* External links */ typo

2023-05-16T16:24:27Z

‎External links: typo

Jnc: /* External links */ A Segmentation Scheme for the PDP-11 Family

2023-05-16T16:24:02Z

‎External links: A Segmentation Scheme for the PDP-11 Family

Jnc: /* Control */ typo

2020-12-30T21:06:54Z

‎Control: typo

Jnc: Other reg names; clarifications

2020-09-12T16:50:48Z

Other reg names; clarifications

Jnc: Mention space vectors come from

2019-01-01T13:12:15Z

Mention space vectors come from

Jnc: /* PARs and PDRs */ +don't cache

2018-07-10T16:10:18Z

‎PARs and PDRs: +don't cache

Jnc: + See also

2018-05-06T16:22:17Z

+ See also

Jnc: Segment/page naming

2018-04-28T17:34:11Z

Segment/page naming

@@ Line 179: / Line 179: @@
 * [[KT11-B Paging Option]] - DEC experiment with paging
 * [[KT11-C Memory Management Unit]] - the archetype
 ==External links==

← Older revision		Revision as of 16:10, 2 July 2023
Line 183:		Line 183:

	* [http://www.bitsavers.org/pdf/dec/pdp11/memos/701014_Segmentation.pdf A Segmentation Scheme for the PDP-11 Family] - interesting design memo		* [http://www.bitsavers.org/pdf/dec/pdp11/memos/701014_Segmentation.pdf A Segmentation Scheme for the PDP-11 Family] - interesting design memo
−
−	~~{{PDP-11}}~~

	[[Category: PDP-11s]]		[[Category: PDP-11s]]

@@ Line 182: / Line 182: @@
 ==External links==
-* [http://www.bitsavers.org/pdf/dec/pdp11/memos/701014_Segmentation.pdf A Segmentation Scheme for the PDP-11 Family - interesting design memo
+* [http://www.bitsavers.org/pdf/dec/pdp11/memos/701014_Segmentation.pdf A Segmentation Scheme for the PDP-11 Family] - interesting design memo
 {{PDP-11}}
 [[Category: PDP-11s]]

@@ Line 179: / Line 179: @@
 * [[KT11-B Paging Option]] - DEC experiment with paging
 * [[KT11-C Memory Management Unit]] - the archetype
 {{PDP-11}}
 [[Category: PDP-11s]]

@@ Line 30: / Line 30: @@
 | 777572 || SSR0 || Control and status
 |-
-| 777574 || SSR1 || Register increment/descrement record
+| 777574 || SSR1 || Register increment/decrement record
 |-
 | 777576 || SSR2 || Virtual address associated with the fault (usually the instruction address)

@@ Line 1: / Line 1: @@
-[[PDP-11]]s which provide [[memory management]] use a standard '''PDP-11 Memory Management''' architecture. When memory management is enabled, the basic 64 Kbyte [[address space]] of the [[PDP-11 architecture]] is divided into 8 '[[segment]]s' (the terminology used in the first version of the documentation; it was later changed to 'pages', for unknown reasons, but this is incorrrect - the functionality provided is that of segmentation, not [[virtual memory|paging]]). Each segment of a virtual address space can be assigned to any location in physical [[main memory]].
+[[PDP-11]]s which provide [[memory management]] use a standard '''PDP-11 Memory Management''' [[architecture]]. When memory management is enabled, the basic 64 Kbyte [[address space]] of the [[PDP-11 architecture]] is divided into 8 '[[segment]]s' (the terminology used in the first version of the documentation; it was later changed to 'pages', for unknown reasons, but this is incorrrect - the functionality provided is that of segmentation, not [[virtual memory|paging]]).
-Each segment can be set to any length between 0 bytes and 8 Kbytes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 [[stack]]s, which typically grow down (from higher addresses to lower).
+Each segment of a virtual address space can be individually assigned to any location in physical [[main memory]]. Each segment can be set to any length between 0 bytes and 8 Kbytes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 [[stack]]s, which typically grow down (from higher addresses to lower).
-The [[Central Processing Unit|CPU]] can be in one of three modes; 'Kernel', 'Supervisor', and 'User'; each has its own separate set of mapping [[register]]s, to provide separate virtual address spaces for each mode.
+The [[Central Processing Unit|CPU]] can be in one of three modes; 'Kernel', 'Supervisor', and 'User'; each has its own separate mappings, to provide separate virtual address spaces for each mode.
-An additional enhancement is that [[instruction]] and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called '''Split I+D space''' capability; this increases the memory available to the operating system, and each user, to 128 Kbytes.
+An additional enhancement is that [[instruction]] and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called '''Split I+D space''' capability; this increases the memory available to the operating system, and each user, to 128 Kbytes. Since immediate operands and absolute addresses are stored contiguous with their instructions, fetches of them are considered to be instruction fetches, for the purposes of deciding which space to use for them.) When split I+D is not enabled in any particular mode, only a single 64 Kbyte address space is provided, using only the I-space registers for that mode.
-(Since immediate operands and absolute addresses are stored contiguous with their instructions, fetches of them are considered to be instruction fetches, for the purposes of deciding which space to use for them.)
+[[Trap]] and [[interrupt vector]]s are fetched from Kernel Data space, when memory management is enabled; this allows bad physical main memory at [[absolute address]] 0 to be bypassed, if it is failing.
 If any instruction causes a [[fault]] (i.e. an attempt to perform a memory operation which cannot be completed, because of the settings of the memory management - e.g. an attempt to write into a segment set as 'read only'), execution of the instruction is aborted, and a memory management trap occurs.
@@ Line 17: / Line 13: @@
 ===Simplified subset===
-A number of the smaller PDP-11's (notably the [[PDP-11/40]], [[PDP-11/34]], [[PDP-11/23]] and [[PDP-11/24]]) provide only a limited subset of the standard memory management facilities. In these machines, there is no support for Split I+D, and no Supervisor mode (just Kernel and User).
+A number of the smaller PDP-11's (notably the [[PDP-11/40]], [[PDP-11/34]], [[PDP-11/60]], [[PDP-11/23]] and [[PDP-11/24]]) provide only a limited subset of the standard memory management facilities. In these machines, there is no support for Split I+D, and no Supervisor mode (just Kernel and User).
-Also, there is no SSR1 register (below), which can make re-starting instructions which cause a fault laborious (the fault-handling code has to decipher the instruction and effectively simulate its operation, to work out which registers need to be 'backed out' to their state before the instruction started execution), and in some cases impossible (e.g. instructions which auto-increment the same register several times).
+Also, there is no SSR1 [[register]] (below), which can make re-starting instructions which cause a fault laborious (the fault-handling code has to decipher the instruction and effectively simulate its operation, to work out which registers need to be 'backed out' to their state before the instruction started execution), and in some cases impossible (e.g. instructions which [[PDP-11 architecture#Addressing modes|auto-increment]] the same register several times).
 ==Registers==
-The memory management is entirely controlled by groups of registers in the CPU (unlike many virtual memory systems, which use page tables held in main memory, and cached in the CPU).
+The memory management is entirely controlled by groups of registers in the CPU (unlike many virtual memory systems, which keep most of the information needed for memory management in page tables held in main memory, and cached in the CPU).
 ===Control===
@@ Line 41: / Line 37: @@
 |}
-On the 'simplified subset' machines, SSR1 and SSR3 are not implemented.
+The names were changed to SR0-SR3 after the 'Segmentation' term was dropped from the name; the forms MMR0-MMR3 are also occasionally met with. On the 'simplified subset' machines, SSR1 and (usually) SSR3 are not implemented (the [[KDF11 CPUs]] are an exception to the latter; see below).
 SSR0 contains control bits (e.g. enabling memory management) and status bits (e.g. information about memory operations which caused a memory management fault, and the segment involved). The layout of SSR0 is:
@@ Line 62: / Line 58: @@
 {{16bit-bitout}}
-The 'Enable 22-bit' bit only applies on machines which support larger memories, i.e. the [[PDP-11/70]], [[PDP-11/44]], and machines with the [[KDF11 CPUs]] and [[KDJ11 CPUs]].
+The 'Enable 22-bit' bit only applies on machines which support larger memories, i.e. the [[PDP-11/70]], [[PDP-11/44]], and machines with the KDF11 CPUs and [[KDJ11 CPUs]].
 ===PARs and PDRs===
@@ Line 181: / Line 177: @@
 ==See also==
-* [[KT11-B Paging Option]] - DEC experiments with paging
+* [[KT11-B Paging Option]] - DEC experiment with paging
-* [[KT11-C Memory Management Unit]] - the arcetype
+* [[KT11-C Memory Management Unit]] - the archetype
 {{PDP-11}}
 [[Category: PDP-11s]]

@@ Line 71: / Line 71: @@
 {{16bit-header}}
-| Unused || colspan=7 | Length || Trapped || Written || colspan=2 | Unused || Direction || colspan=3 | Access Control
+| Don't Cache || colspan=7 | Length || Trapped || Written || colspan=2 | Unused || Direction || colspan=3 | Access Control
 {{16bit-bitout}}
@@ Line 96: / Line 96: @@
 On the 'simplified subset' machines, only modes 0, 2 and 6 are supported, and neither is the 'Trapped' bit (set on PDR's for memory references that trapped, on the other machines).
 The addresses of the PAR/PDR sets are:

← Older revision		Revision as of 17:34, 28 April 2018
Line 1:		Line 1:
−	[[PDP-11]]s which provide [[memory management]] use a standard '''PDP-11 Memory Management''' architecture. When memory management is enabled, the basic 64 Kbyte [[address space]] of the [[PDP-11 architecture]] is divided into 8 '''~~segments~~'~~''; each~~ segment of ~~the~~ virtual address space can be assigned to any location in physical [[main memory]].	+	[[PDP-11]]s which provide [[memory management]] use a standard '''PDP-11 Memory Management''' architecture. When memory management is enabled, the basic 64 Kbyte [[address space]] of the [[PDP-11 architecture]] is divided into 8 '[[segment]]s' (the terminology used in the first version of the documentation; it was later changed to 'pages', for unknown reasons, but this is incorrrect - the functionality provided is that of segmentation, not [[virtual memory\|paging]]). Each segment of a virtual address space can be assigned to any location in physical [[main memory]].

	Each segment can be set to any length between 0 bytes and 8 Kbytes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 [[stack]]s, which typically grow down (from higher addresses to lower).		Each segment can be set to any length between 0 bytes and 8 Kbytes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 [[stack]]s, which typically grow down (from higher addresses to lower).