PDP-11 architecture - Revision history

Jnc: /* External links */ +A Case Study of How Not to Design Condition Codes

2024-07-23T14:23:31Z

‎External links: +A Case Study of How Not to Design Condition Codes

Jnc: /* External links */ +PDP11 Programming Card

2024-02-29T15:37:03Z

‎External links: +PDP11 Programming Card

Jnc: /* See also */ +PDP-11 stacks

2023-06-13T18:45:07Z

‎See also: +PDP-11 stacks

Jnc: /* Processor Status Word */ minor clarifications

2022-08-30T01:06:31Z

‎Processor Status Word: minor clarifications

Jnc: /* Addressing modes */ +clarifications

2022-01-04T10:23:53Z

‎Addressing modes: +clarifications

Mharriger: Fix bad internal link syntax

2022-01-04T03:30:32Z

Fix bad internal link syntax

Jnc: /* See also */ +1

2020-12-26T00:08:00Z

‎See also: +1

Jnc: Add extrabPS bit example; rm dup links

2020-09-11T15:24:16Z

Add extrabPS bit example; rm dup links

Jnc: +PSW

2020-09-10T20:51:22Z

+PSW

Jnc: /* Addressing modes */ clarify order of autodecrement

2020-09-08T16:21:03Z

‎Addressing modes: clarify order of autodecrement

@@ Line 210: / Line 210: @@
 * [http://ftp.dbit.com/pub/pdp11/faq/faq.pages/PDPinst.html What is the PDP-11 instruction set?]
 * [http://www.jfc.org.uk/documents/scandoc.php?dir=pdp11/pdp11 Digital PDP11 Programming Card]
 {{PDP-11}}

@@ Line 204: / Line 204: @@
 * [[UNIBUS map]]
 * [[PDP-11 family differences appendix]]
 {{PDP-11}}

@@ Line 201: / Line 201: @@
 * [[PDP-11 Extended Instruction Set]]
 * [[PDP-11 Commercial Instruction Set]]
 * [[UNIBUS map]]
 * [[PDP-11 family differences appendix]]

@@ Line 170: / Line 170: @@
 ==Processor Status Word==
-All PDP-11's have a Processor Status Word register.The contents vary from model to model, but in all of the it contains the four condition code bits; a bit to control 'trace' traps (which allow [[single-step]]ping the CPU); and the CPU's current [[priority]] level (to allow or defer peripheral interrupts). On models which provide memory management, there are two fields to specify the current and previous [[PDP-11 Memory Management|modes]]. Some models provide two sets of general CPU registers (only one may be in use at any time); a bit in the PSW selects which one is in use.
+All PDP-11's have a Processor Status Word register.The contents vary from model to model, but in all of them it contains: the four condition code bits; a bit to control 'trace' traps (which allow [[single-step]]ping the CPU); and the CPU's current [[priority]] level (to allow or defer peripheral interrupts). On models which provide memory management, there are two fields to specify the current and previous [[PDP-11 Memory Management|modes]]. Some models provide two sets of general CPU registers (only one may be in use at any time); in those machines, a bit in the PSW selects which one is in use.
 The layout of the PSW is:
@@ Line 179: / Line 179: @@
 Some of the 'unused' bits (above) have uses on particular models; for example, in the -11/44's [[KD11-Z CPU]], bit 8 is used to indicate that a Commercial Instruction Set instruction is in process, but not completed (visible when the PS is saved in an interrupt).
-The PSW appears at address 0177776 on most models (0777776 on the UNIBUS, in models with a UNIBUS); the sole exception is the  LSI11 CPUs, on which it can only be read/written directly with the MFPS/MTPS instructions (which appear on some, but not all, models).
+The PSW appears at address 0177776 on most models (0777776 on the UNIBUS, in models with a UNIBUS); the sole exception is the LSI11 CPUs, on which it can only be read/written directly with the MFPS/MTPS instructions (which appear on some, but not all, models).
 Depending on the CPU's model (and current mode, for those which support multiple modes), not all bits can be written directly, though. Consult the "PDP-11 Family Differences" appendix, in the ''PDP-11 Architecture Handbook'' (1983-84 version) or the ''MICRO/PDP-11 Handbook'' (1983-84 version) for details.

@@ Line 61: / Line 61: @@
 |}
-and the indirect modes are:
+(in the last, X is the word after the instruction), and the indirect modes are:
 {| border=1
@@ Line 77: / Line 77: @@
 As mentioned, auto-increment and auto-decrement allow any register to be used as a stack pointer, but the hardware enforces the use of R6 as the SP, so it is un-common for another register to be used for this.
-Note that when destination operands use auto-increment or auto-decrement mode, the modification is only made on the first use of the operand; the second uses the same address as that used by the first. (This makes sense; the [[microcode]] (or [[state machine]], in the [[KA11 CPU]]) calculates the address of the second operand once, and saves that address in a temporary register - usually, but not necessarily, the Bus Address Register. Then, for the write, it just re-uses that value.)
+Note that when destination operands use auto-increment or auto-decrement mode, the modification is only made on the first use of the operand; the second uses the same address as that used by the first. (This makes sense; the [[microcode]] (or [[state machine]], in the [[KA11 CPU]]) calculates the address of the second operand once, and saves that address in a temporary register - usually, but not necessarily, the [[Bus Address Register]]. Then, for the write, it just re-uses that value.)
-The use of auto-increment mode with the PC provides literal operands (both immediate, and absolute addresses); indexed modes with the PC can be used for [[location-independent code]].
+The use of auto-increment mode with the PC as the register used provides literal operands (both immediate, and absolute addresses); indexed modes with the PC can be used for [[location-independent code]].
 ==Instruction set==

@@ Line 3: / Line 3: @@
 The [[Central Processing Unit|CPU]] had 8 [[general register|general purpose registers]]; the [[operand]] coding, which was applied regularly across essentially the entire [[instruction set]], allowed it to provide a two-[[address]] instruction [[architecture]], not a simple [[load-store architecture]] like its predecessor, the 12-bit [[PDP-8 family|PDP-8]].
-One of the [[register]]s (R7) was dedicated to be the [[Program Counter]], and one (R6) was more or less dedicated to be the [[Stack Pointer]]. (Other registers can be used as [[stack]] [[pointer]]s, but the hardware uses this one for [[subroutine]] call and return, [[interrupt]]s, [[trap]]s, etc.) (There are a number of sometimes poorly-documented details of PDP-11 stack operation; see [PDP-11 stacks|here]] for more.)
+One of the [[register]]s (R7) was dedicated to be the [[Program Counter]], and one (R6) was more or less dedicated to be the [[Stack Pointer]]. (Other registers can be used as [[stack]] [[pointer]]s, but the hardware uses this one for [[subroutine]] call and return, [[interrupt]]s, [[trap]]s, etc.) (There are a number of sometimes poorly-documented details of PDP-11 stack operation; see [[PDP-11 stacks|here]] for more.)
 These registers, along with a variety of register-based addressing modes, allowed it to provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on a machine which had only 16-bit [[word]]s (and thus [[instruction]]s).

@@ Line 3: / Line 3: @@
 The [[Central Processing Unit|CPU]] had 8 [[general register|general purpose registers]]; the [[operand]] coding, which was applied regularly across essentially the entire [[instruction set]], allowed it to provide a two-[[address]] instruction [[architecture]], not a simple [[load-store architecture]] like its predecessor, the 12-bit [[PDP-8 family|PDP-8]].
-One of the [[register]]s (R7) was dedicated to be the [[Program Counter]], and one (R6) was more or less dedicated to be the [[Stack Pointer]]. (Other registers can be used as [[stack]] [[pointer]]s, but the hardware uses this one for [[subroutine]] call and return, [[interrupt]]s, [[trap]]s, etc.) There are a number of sometimes poorly-documented details of PDP-11 stack operation; see [PDP-11 stacks|here]] for more.
+One of the [[register]]s (R7) was dedicated to be the [[Program Counter]], and one (R6) was more or less dedicated to be the [[Stack Pointer]]. (Other registers can be used as [[stack]] [[pointer]]s, but the hardware uses this one for [[subroutine]] call and return, [[interrupt]]s, [[trap]]s, etc.) (There are a number of sometimes poorly-documented details of PDP-11 stack operation; see [PDP-11 stacks|here]] for more.)
 These registers, along with a variety of register-based addressing modes, allowed it to provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on a machine which had only 16-bit [[word]]s (and thus [[instruction]]s).
-The regular application of the operand coding across essentially the entire instruction set allowed these additional operand types to be widely available; this, and the power of the large range of operand modes, substantially reduced the code size.
+The regular application of the operand coding across essentially the entire instruction set allowed these additional operand types to be widely available; this, and the power of the large range of operand modes, substantially reduced the code size. This was an important consideration both in the PDP-11's early life, when small and expensive [[core memory]] was the standard main memory; and in its later life, when the 16-bit address space became a severe limit.
 Most instructions come in both [[byte]] and [[word]] data forms; an exception is ADD and SUB, which exist in only word forms (probably because there was not enough room in the instruction set to have them both in both forms).
-On CPU models intended for use in time-sharing systems, two CPU modes, [[Kernel]] and [[User]], were supported, along with [[memory management]].
+On CPU models intended for use in [[time-sharing]] systems, two CPU modes, [[Kernel]] and [[User]], were supported, along with [[memory management]].
 Early PDP-11's were all built around the [[UNIBUS]] [[bus]]; later models switched to the [[QBUS]], which used less pins.
@@ Line 19: / Line 17: @@
 ==Extensions==
-The first PDP-11 (the [[PDP-11/20]]) was limited to one-bit shift operations, and did not have hardware integer multiplication or division, or any hardware [[floating point]]. (An option, the [[KE11-A Extended Arithmetic Element]], did provide multiply, etc in hardware, but it was a separate [[peripheral]] on the UNIBUS, not part of the CPU.)
+The first PDP-11 (the [[PDP-11/20]]) was limited to one-bit shift operations, and did not have hardware integer multiplication or division, or any hardware [[floating point]]. (An option, the [[KE11-A Extended Arithmetic Element]], did provide multiply, divide, etc in hardware, but it was a separate [[peripheral]] on the UNIBUS, not part of the CPU.)
-The next model, the [[PDP-11/45]], added both of these (the latter as an option), although the follow-on low-cost machines, the [[PDP-11/05]] and [[PDP-11/04]], again did not have either.
+The next model, the [[PDP-11/45]], added both of these classes (the latter as an option), although the follow-on low-cost machines, the [[PDP-11/05]] and [[PDP-11/04]], again did not have either.
-Later machines tended to include the former group - although on some early mid-range machines such as the [[PDP-11/40]] and [[PDP-11/03]], they were only an [[PDP-11 Extended Instruction Set|option]]. Floating point was also added to the later machines (although only as an option, until relatively late in the line).
+Later machines tended to include the former group - although on some early mid-range machines such as the [[PDP-11/40]] and [[LSI-11s]], they were only an [[PDP-11 Extended Instruction Set|option]]. Floating point was also added to the later machines (although only as an option, until relatively late in the line).
 Late in the PDP-11 family's lifetime, a [[Commercial Instruction Set]] was defined, and made available as an [[PDP-11 Commercial Instruction Set|option]] in some of the later machines.
@@ Line 29: / Line 27: @@
 ===Floating point===
-Two forms of floating point were added: a simplified form, [[FIS floating point]], with only the 4 basic operations, using 32-bit variables, in a few early machines; and full-blown floating point (32-bit and 64-bit formats, many operations), [[FP11 floating point]].
+Two forms of floating point were added: a simplified form, [[FIS floating point]], with only the 4 basic operations, using 32-bit data, in a few early machines; and full-blown floating point (32-bit and 64-bit formats, many operations), [[FP11 floating point]].
 The former was available as an option in the PDP-11/40, and later in the PDP-11/03. The latter was available as an option in the [[PDP-11/45]] and variants thereof (the [[PDP-11/50]] and [[PDP-11/55]]), the [[PDP-11/70]], [[PDP-11/34]], [[PDP-11/44]] and [[PDP-11/23]]; it was standard in the [[KDJ11 CPUs]] (although in these machines an optional [[FPJ11 floating point accelerator]] greatly improved the floating point performance).
@@ Line 35: / Line 33: @@
 ===Memory management and CPU modes===
-After a few disparate custom add-on units to provide memory management and CPU modes in the [[PDP-11/20]], they became [[PDP-11 Memory Management|standardized]] with the PDP-11/45 (in which memory management was an option); most later machines supported them. A simplified version was supported in the -11/40 and -11/23 (as an option, in both), and in the -11/34 (standard).
+After a few disparate custom add-on units to provide memory management and CPU modes in the [[PDP-11/20]], they became [[PDP-11 Memory Management|standardized]] with the PDP-11/45 (in which memory management was an option); most later machines supported them. A simplified version was supported in the -11/40 and -11/23 (as an option, in both), and in the -11/34 (standard) and [[PDP-11/60]] (the lack of the full-blown version was a significant handicap in what was a relatively high-end machine).
 ==Operands==
@@ Line 172: / Line 170: @@
 ==Processor Status Word==
-All PDP-11's have a [[Processor Status Word]] register.The contents vary from model to model, but in all of the it contains the four [[condition codes|condition code bits]]; a bit to control 'trace' [[trap]]s (which allow [[single-step]]ping the CPU); and the CPU's current [[priority]] level (to allow or defer [[peripheral]] [[interrupt]]s). On models which provide [[memory management]], there are two fields to specify the current and previous [[PDP-11 Memory Management|modes]]. Some models provide two sets of general CPU registers (only one may be in use at any time); a bit in the PSW selects which one is in use.
+All PDP-11's have a Processor Status Word register.The contents vary from model to model, but in all of the it contains the four condition code bits; a bit to control 'trace' traps (which allow [[single-step]]ping the CPU); and the CPU's current [[priority]] level (to allow or defer peripheral interrupts). On models which provide memory management, there are two fields to specify the current and previous [[PDP-11 Memory Management|modes]]. Some models provide two sets of general CPU registers (only one may be in use at any time); a bit in the PSW selects which one is in use.
 The layout of the PSW is:
@@ Line 179: / Line 177: @@
 {{16bit-bitout}}
-Some of the 'unused' bits (above) have uses on particular models.
+Some of the 'unused' bits (above) have uses on particular models; for example, in the -11/44's [[KD11-Z CPU]], bit 8 is used to indicate that a Commercial Instruction Set instruction is in process, but not completed (visible when the PS is saved in an interrupt).
-The PSW appears at address 0177776 on most models (0777776 on the UNIBUS, in models with a UNIBUS); the sole exception is the  [[LSI11 CPUs]], on which it can only be read/written directly with the MFPS/MTPS instructions (which appear on some, but not all, models).
+The PSW appears at address 0177776 on most models (0777776 on the UNIBUS, in models with a UNIBUS); the sole exception is the  LSI11 CPUs, on which it can only be read/written directly with the MFPS/MTPS instructions (which appear on some, but not all, models).
 Depending on the CPU's model (and current mode, for those which support multiple modes), not all bits can be written directly, though. Consult the "PDP-11 Family Differences" appendix, in the ''PDP-11 Architecture Handbook'' (1983-84 version) or the ''MICRO/PDP-11 Handbook'' (1983-84 version) for details.

@@ Line 56: / Line 56: @@
 |0      || Register                     || R            || (R) is the operand
 |-
-|2      || Auto-increment               || (R)+         || (R) is the address; (R) is incremented by 1 or 2, in case of byte or word instructions.
+|2      || Auto-increment               || (R)+         || (R) is the address; (R) is then incremented by 1 or 2, in case of byte or word instructions.
 |-
-|4      || Auto-decrement               || (R)-         || (R) is decremented by 1 or 2, in case of byte or word instructions; R is address.
+|4      || Auto-decrement               || -(R)         || (R) is decremented by 1 or 2, in case of byte or word instructions; R is then the address.
 |-
 |6      || Index                        || X(R)         || (R) + X is the address.
@@ Line 70: / Line 70: @@
 |1      || Register deferred            || @R or (R)    || (R) contains address of operand
 |-
-|3      || Auto-increment deferred      || @(R)+        || (R) is the address of the address; (R) is incremented by 2
+|3      || Auto-increment deferred      || @(R)+        || (R) is the address of the address; (R) is then incremented by 2
 |-
-|5      || Auto-decrement deferred      || @(R)-        || (R) is decremented by two; (R) is the address of the address.
+|5      || Auto-decrement deferred      || @-(R)        || (R) is decremented by two; (R) is then the address of the address.
 |-
 |7      || Index deferred               || @X(R)        || (R) + X is the address of the address