PDP-11 family differences appendix - Revision history

Jnc: +Simple MMU w/ SSR3

2020-09-13T01:12:24Z

+Simple MMU w/ SSR3

Jnc: +per-segment caching

2020-09-12T23:00:05Z

+per-segment caching

Jnc: +SSR1

2020-09-12T12:55:59Z

+SSR1

Jnc: Start, more to come

2020-09-08T00:57:53Z

Start, more to come

New page

The ''[[PDP-11]] [[Architecture]] Handbook'' (1983-84 version) contains a "PDP-11 Family Differences" appendix (re-printed in the ''MICRO/PDP-11 Handbook'', 1983-84 version) which lays out in tabular form the few ways, and PDP-11 models, which vary from each other in the fine details of their behavior. (Had [[Digital Equipment Corporation|DEC]] formalized the [[PDP-11 architecture]] earlier, these might not have happened, but once the products had made their way to customers, the die was cast.)

A few other minor inter-model differences have been discovered: they are given in a similar tabular form (with pairs of rows for each idiosyncrasy) here:

{| class="wikitable"
! Item !! 03 !! 23/24 !! 73/83/93 !! 04 !! 05 !! 20 !! 34 !! 40 !! 44 !! 45 !! 70
|-
| The SXT [[instruction]] clears the 'V' [[condition codes|bit]] || @ || @ || @ || @ || @ || - || @ || || @ || @ || @
|-
| SXT - 'V' bit unaffected || || || || || || - || || @ || || ||
|}

An '@' indicates that the manuals for this CPU indicate that it operates in the manner stated; a '%' indicates that this behaviour has been confirmed by testing. A blank entry in both rows of the pair indicates that the behavior of this model is unknown; a '-' indicates that this model does not support that instruction.

The [[Central Processing Unit|CPU]] models referred to in each of the columns above are:

{| class="wikitable"
! Model !! CPU
|-
| 03 || [[LSI11 CPUs]]
|-
| 23/24 || [[KDF11 CPUs]]
|-
| 73/83/93 || [[KDJ11 CPUs]]
|-
| 04 || [[KD11-D CPU]]
|-
| 05 || [[KD11-B CPU]]
|-
| 20 || [[KA11 CPU]]
|-
| 34 || [[KD11-E CPU]]/[[KD11-EA CPU]]
|-
| 40 || [[KD11-A CPU]]
|-
| 44 || [[KD11-Z CPU]]
|-
| 45 || [[KB11-A CPU]]/[[KB11-D CPU]]/
|-
| 70 || [[KB11-B CPU]]/ [[KB11-C CPU]]/
|}

{{PDP-11}}

[[Category: PDP-11s]]

@@ Line 1: / Line 1: @@
 The ''[[PDP-11]] [[Architecture]] Handbook'' (1983-84 version) contains a "PDP-11 Family Differences" appendix (re-printed in the ''MICRO/PDP-11 Handbook'', 1983-84 version) which lays out in tabular form the few ways, and the models involved, which vary from each other in the fine details of their behavior. (Had [[Digital Equipment Corporation|DEC]] formalized the [[PDP-11 architecture]] earlier, these might not have happened, but once the products had made their way to customers, the die was cast.)
-A few other minor inter-model differences have been discovered: they are given in a similar tabular form (with groups of rows for each idiosyncrasy) here:
+A few other minor inter-model differences (some well-documented, some not) have been discovered: they are given in a similar tabular form (with groups of rows for each idiosyncrasy) here:
 {| class="wikitable"
@@ Line 10: / Line 10: @@
 | SXT - 'V' bit unaffected || || || || || || - || || @ || || ||
 |-
-| Blank [[PDP-11 Memory Management|SSR1]] register || - || % || - || - || - || - || @ || || - || - || -
+| Blank [[PDP-11 Memory Management#Control|SSR1]] [[register]] || - || % || - || - || - || - || @ || || - || - || -
 |-
 | No SSR1 || - || || - || - || - || - || || @ || - || - || -
 |-
 | Explicit [[cache|caching]] control per-[[segment]] || - || - || @ || - || - || - ||  || - || || - ||

@@ Line 13: / Line 13: @@
 |-
 | No SSR1 || - || || - || - || - || - || || @ || - || - || -
 |}

@@ Line 1: / Line 1: @@
-The ''[[PDP-11]] [[Architecture]] Handbook'' (1983-84 version) contains a "PDP-11 Family Differences" appendix (re-printed in the ''MICRO/PDP-11 Handbook'', 1983-84 version) which lays out in tabular form the few ways, and PDP-11 models, which vary from each other in the fine details of their behavior. (Had [[Digital Equipment Corporation|DEC]] formalized the [[PDP-11 architecture]] earlier, these might not have happened, but once the products had made their way to customers, the die was cast.)
+The ''[[PDP-11]] [[Architecture]] Handbook'' (1983-84 version) contains a "PDP-11 Family Differences" appendix (re-printed in the ''MICRO/PDP-11 Handbook'', 1983-84 version) which lays out in tabular form the few ways, and the models involved, which vary from each other in the fine details of their behavior. (Had [[Digital Equipment Corporation|DEC]] formalized the [[PDP-11 architecture]] earlier, these might not have happened, but once the products had made their way to customers, the die was cast.)
-A few other minor inter-model differences have been discovered: they are given in a similar tabular form (with pairs of rows for each idiosyncrasy) here:
+A few other minor inter-model differences have been discovered: they are given in a similar tabular form (with groups of rows for each idiosyncrasy) here:
 {| class="wikitable"
 ! Item !! 03 !! 23/24 !! 73/83/93 !! 04 !! 05 !! 20 !! 34 !! 40 !! 44 !! 45 !! 70
 |-
-| The SXT [[instruction]] clears the 'V' [[condition codes|bit]] || @ || @ || @ || @ || @ || - || @ || || @ || @ || @
+| The SXT [[instruction]] clears the 'V' [[condition codes|bit]] || % || @ || @ || @ || @ || - || @ || || @ || @ || @
 |-
 | SXT - 'V' bit unaffected || || || || || || - || || @ || || ||
 |}
-An '@' indicates that the manuals for this CPU indicate that it operates in the manner stated; a '%' indicates that this behaviour has been confirmed by testing. A blank entry in both rows of the pair indicates that the behavior of this model is unknown; a '-' indicates that this model does not support that instruction.
+An '@' indicates that the manuals for this CPU indicate that it operates in the manner stated; a '%' indicates that this behaviour has been confirmed by testing. A blank entry in both rows of the pair indicates that the behavior of this model is unknown; a '-' indicates that this model does not support that instruction, or is otherwise inapplicable.
 The [[Central Processing Unit|CPU]] models referred to in each of the columns above are: