PDP-11 stacks - Revision history

Jnc: /* Red/Yellow Zones and Stack Limit Registers */ no recursive violations

2022-10-14T10:14:02Z

Red/Yellow Zones and Stack Limit Registers: no recursive violations

← Older revision		Revision as of 10:14, 14 October 2022
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	===Red/Yellow Zones and Stack Limit Registers===		===Red/Yellow Zones and Stack Limit Registers===

	The most complex stack overflow protection mechanism first appeared in the [[KB11-A CPU]] of the [[PDP-11/45]]. In Kernel mode, it had a 'two-zone' scheme: ~~the~~ 'Yellow Zone' is a 16-word grace area, in which operations (either a 'push' by an instruction, or the pushes caused by a trap or an interrupt) were allowed, but result in a trap after the operation is completed~~; in~~ the 'Red Zone', all operations are prohibited, and result in aborting of the operation, and an immediate trap, as below.		The most complex stack overflow protection mechanism first appeared in the [[KB11-A CPU]] of the [[PDP-11/45]]. In Kernel mode, it had a 'two-zone' scheme:

			* The 'Yellow Zone' is a 16-word grace area, in which operations (either a 'push' by an instruction, or the pushes caused by the saving of the previous PC and PS in a trap or an interrupt) were allowed, but result in a trap after the operation is completed
			* In the 'Red Zone', all operations are prohibited, and result in aborting of the operation, and an immediate trap, as below.

			When a Yellow Zone trap occurs, further Yellow Zone violations are suppressed for the push of the previous PC and PS (since otherwise recursive violations would be caused by attempting to take the trap). However, the trap handler must not attempt to push anything onto the existing stack, since doing so could cause yet another violation, and resultant trap.

	When Red Zone violations occur, the SP is set to 4; the previous PC and PS are then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses, and use of non-existent memory, result in identical handling.)		When Red Zone violations occur, the SP is set to 4; the previous PC and PS are then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses, and use of non-existent memory, result in identical handling.)

Jnc: /* Red/Yellow Zones and Stack Limit Registers */ op is an inst or a trap/int

2022-10-13T23:35:30Z

Red/Yellow Zones and Stack Limit Registers: op is an inst or a trap/int

← Older revision		Revision as of 23:35, 13 October 2022
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	===Red/Yellow Zones and Stack Limit Registers===		===Red/Yellow Zones and Stack Limit Registers===

	The most complex stack overflow protection mechanism first appeared in the [[KB11-A CPU]] of the [[PDP-11/45]]. In Kernel mode, it had a 'two-zone' scheme: the 'Yellow Zone' is a 16-word grace area, in which operations were allowed, but result in a trap after the operation is completed; in the 'Red Zone', all operations are prohibited, and result in aborting of the operation, and an immediate trap.		The most complex stack overflow protection mechanism first appeared in the [[KB11-A CPU]] of the [[PDP-11/45]]. In Kernel mode, it had a 'two-zone' scheme: the 'Yellow Zone' is a 16-word grace area, in which operations (either a 'push' by an instruction, or the pushes caused by a trap or an interrupt) were allowed, but result in a trap after the operation is completed; in the 'Red Zone', all operations are prohibited, and result in aborting of the operation, and an immediate trap, as below.

	When Red Zone violations occur, the SP is set to 4; the previous PC and PS are then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses, and use of non-existent memory, result in identical handling.)		When Red Zone violations occur, the SP is set to 4; the previous PC and PS are then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses, and use of non-existent memory, result in identical handling.)

	The address of the stack limit can be set with the Stack Limit Register in the CPU. It is a word [[register]] (at 0777774), but the bottom byte is unused; it is cleared by a reset (e.g. when starting the CPU). The Red Zone runs up through the address given there plus 0337; the Yellow Zone starts at 0340, and runs up through 0377.		The address of the stack limit can be set with the Stack Limit Register in the CPU. It is a word [[register]] (at 0777774), but the bottom byte is unused; it is cleared by a reset (e.g. when starting the CPU). The Red Zone runs up through the address given there plus 0337; the Yellow Zone starts at that address plus 0340, and runs up through plus 0377.

	In User mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.		In User mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.
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	The [[KD11-A CPU]] of the [[PDP-11/40]] has the two-zone stack limitation as above, but at a fixed address of 0400. A similar Stack Limit Register is available as an option, the [[KJ11-A Stack Limit Register]]; when present, it functions identically to the others.		The [[KD11-A CPU]] of the [[PDP-11/40]] has the two-zone stack limitation as above, but at a fixed address of 0400. A similar Stack Limit Register is available as an option, the [[KJ11-A Stack Limit Register]]; when present, it functions identically to the others.

	~~The [[KD11-K CPU]] of the [[PDP-11/60]] also has Red and Yellow Zones, and a Stack Limit Register, which operate the same as above.~~

	{{PDP-11}}		{{PDP-11}}

	[[Category: PDP-11s]]		[[Category: PDP-11s]]

Jnc: /* Red/Yellow Zones and Stack Limit Registers */ Also the PDP-11/60

2022-01-11T21:33:05Z

Red/Yellow Zones and Stack Limit Registers: Also the PDP-11/60

← Older revision		Revision as of 21:33, 11 January 2022
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	The [[KD11-A CPU]] of the [[PDP-11/40]] has the two-zone stack limitation as above, but at a fixed address of 0400. A similar Stack Limit Register is available as an option, the [[KJ11-A Stack Limit Register]]; when present, it functions identically to the others.		The [[KD11-A CPU]] of the [[PDP-11/40]] has the two-zone stack limitation as above, but at a fixed address of 0400. A similar Stack Limit Register is available as an option, the [[KJ11-A Stack Limit Register]]; when present, it functions identically to the others.

			The [[KD11-K CPU]] of the [[PDP-11/60]] also has Red and Yellow Zones, and a Stack Limit Register, which operate the same as above.

	{{PDP-11}}		{{PDP-11}}

	[[Category: PDP-11s]]		[[Category: PDP-11s]]

Jnc: /* Stack limits */ Kernel mode only

2020-09-12T23:09:09Z

Stack limits: Kernel mode only

← Older revision		Revision as of 23:09, 12 September 2020
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	==Stack limits==		==Stack limits==

	Almost all PDP-11 CPU models have some form of stack overflow protection, which causes a CPU trap when the stack overflows. (LSI-11 CPUs have no overflow detection.) The details of the mechanism vary from model to model; unfortunately, the details are often documented poorly, or not at all.		Almost all PDP-11 CPU models have some form of stack overflow protection (in [[PDP-11 Memory Management\|kernel mode]] only, for the models which support modes), which causes a CPU trap when the stack overflows. (LSI-11 CPUs have no overflow detection.) The details of the mechanism vary from model to model; unfortunately, the details are often documented poorly, or not at all.

	===Fixed limit===		===Fixed limit===

Jnc: minor copyedits, rm dup links

2020-09-04T18:58:01Z

minor copyedits, rm dup links

Jnc: Consolidate stack details

2020-06-20T15:07:34Z

Consolidate stack details

← Older revision		Revision as of 15:07, 20 June 2020
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	~~Almost all~~ [[PDP-11]] ~~[[Central Processing Unit\|CPU]] models have some form~~ of [[stack]] ~~overflow protection~~, which ~~causes a CPU [[trap]] when~~ the ~~stack overflows. (~~[[~~LSI~~-11 ~~CPUs~~]] ~~have no overflow detection~~.~~) The~~ details of the ~~mechanism vary from model~~ to ~~model; unfortunately, the details are often documented poorly, or not at all~~.		The [[PDP-11]] makes heavy use of [[stack]]s, for which it has good support via the auto-increment and auto-decrement [[PDP-11 architecture#Addressing modes\|addressing modes]]. However, there are a number of sometimes poorly-documented details of their operation, which ward off potential issues with the main stack (pointed to by R6).

	~~==Fixed Limit==~~		* [[Byte]] operations (push and pop) on the R6 stack always adjust the [[Stack Pointer]] by 2, not 1; this to ensure that it always contains a [[word]] [[address]], should an un-expected [[interrupt]] or [[trap]] require it to be used to save the old [[Processor Status Word\|PS]] and [[Program Counter\|PC]].

	~~The first PDP-11 CPU, the~~ [[~~KA11~~ CPU]] ~~of the~~ [[~~PDP~~-~~11/20~~]], ~~had a fixed~~ [[~~address~~]] ~~limit of 0400; if~~ the ~~stack went below this~~, ~~a trap occurred after~~ the ~~offending operation (~~[[~~instruction~~]], trap, and ~~probably also [[interrupt]]) was over~~.		* On [[Central Processing Unit\|CPU]] models intended for use in [[time-sharing]] systems, which support [[User]] and [[Kernel]] modes, there are separate R6's for the two modes, so that the [[operating system]] can use the latter one for interrupt and trap handling, and thereby guarantee that the user cannot derange R6's contents before it needs to be used.

	~~The [[KD11-B CPU]]~~ of the ~~[[PDP-11/05]] did the exact same thing; as do the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]]~~ (~~see EK-KD1EA-MM-001, pg. 2-33~~). ~~[[KDF11 CPUs]] have the same mechanism (definitely on interrupts, as well~~; ~~two [[Processor Status Word\|PS]]/[[Program Counter\|PC]] pairs, one from the interrupt, and one from the trap, are pushed when this happens)~~.		* Almost all models have some form of stack address limitation, which causes a trap when the stack overflows (or tries to). The details vary from model to model; see below for details.

	[[~~KDJ11 CPUs~~]] ~~have a similar mechanism~~, ~~but although their CPU Error Register has separate Red~~ and ~~Yellow bits~~ (~~below~~), ~~interrupts when~~ the ~~SP is set below 0400 only set the Yellow bit~~, and ~~push both PS/PC pairs; only a fault on the interrupt push causes~~ the ~~Red~~ bit ~~to be set, and then only the interrupt PS/PC are saved (~~in 0~~/2; see~~ [[~~PDP~~-11 ~~architecture#Stack special-casing\|here~~]]).		* When an interrupt or trap occurs, if R6 does contain either an odd (i.e. non-word) address, or an address which does not point to functional [[main memory]], on many models R6 is then bashed to contain 4, after which the old PC and PS are saved in 0 and 2 (respectively); after that, the CPU takes an odd-address/non-existent-memory trap. ([[KDF11 CPUs]] ignore odd stack addresses, and proceed as if the bottom address bit in them is 0. Apparently [[LSI-11 CPUs]] also ignores odd stack addresses.)

	~~==Red~~/~~Yellow Zones~~ and ~~Stack Limit Registers==~~		: On the [[KA11 CPU]] ([[PDP-11/20]]), [[KD11-B CPU]] ([[PDP-11/05]]), [[KD11-D CPU]] ([[PDP-11/04]]), [[KD11-E CPU]] ([[PDP-11/34]]), [[KD11-Z CPU]] ([[PDP-11/44]]), and LSI-11 CPUs, a fault during a trap will halt the CPU.

	The most complex stack overflow protection mechanism first appeared in the [[KB11-A CPU]] of the [[PDP-11/45]]. In [[Kernel]] mode, it had a 'two-zone' scheme: the 'Yellow Zone' is a 16-[[word]] grace area, in which operations were allowed, but result in a trap after the operation is completed; in the 'Red Zone', all operations are prohibited, and result in aborting of the operation, and an immediate trap.		==Stack limits==

	~~When Red Zone violations occur~~, the [[~~Stack Pointer~~]] ~~is set~~ to 4; the ~~previous PC and PS~~ are ~~then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses~~, ~~and use of non-existent memory, result in identical handling~~.)		Almost all PDP-11 CPU models have some form of stack overflow protection, which causes a CPU trap when the stack overflows. ([[LSI-11 CPUs]] have no overflow detection.) The details of the mechanism vary from model to model; unfortunately, the details are often documented poorly, or not at all.

	~~The [[address]] of the stack~~ limit can be set with the Stack Limit Register [[register]] in the CPU. It is a word register (at 0777774), but the bottom [[byte]] is unused; it is cleared by a reset (e.g. when starting the CPU). The Red Zone runs up through the address given there plus 0337; the Yellow Zone starts at 0340, and runs up through 0377.		===Fixed limit===

	In [[~~User~~]] mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.		The first PDP-11 CPU, the [[KA11 CPU]] of the [[PDP-11/20]], had a fixed address limit of 0400; if the stack went below this, a trap occurred after the offending operation ([[instruction]], trap, and probably also interrupt) was over.

			The [[KD11-B CPU]] of the [[PDP-11/05]] did the exact same thing; as do the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]] (see EK-KD1EA-MM-001, pg. 2-33). [[KDF11 CPUs]] have the same mechanism (definitely on interrupts, as well; two PS/PC pairs, one from the interrupt, and one from the trap, are pushed when this happens).

			[[KDJ11 CPUs]] have a similar mechanism, but although their CPU Error Register has separate Red and Yellow bits (below), interrupts when the SP is set below 0400 only set the Yellow bit, and push both PS/PC pairs. Only a fault on the interrupt push causes the Red bit to be set, and then only the interrupt PS/PC are saved (in 0/2; see above for more).

			===Red/Yellow Zones and Stack Limit Registers===

			The most complex stack overflow protection mechanism first appeared in the [[KB11-A CPU]] of the [[PDP-11/45]]. In Kernel mode, it had a 'two-zone' scheme: the 'Yellow Zone' is a 16-word grace area, in which operations were allowed, but result in a trap after the operation is completed; in the 'Red Zone', all operations are prohibited, and result in aborting of the operation, and an immediate trap.

			When Red Zone violations occur, the SP is set to 4; the previous PC and PS are then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses, and use of non-existent memory, result in identical handling.)

			The address of the stack limit can be set with the Stack Limit Register [[register]] in the CPU. It is a word register (at 0777774), but the bottom byte is unused; it is cleared by a reset (e.g. when starting the CPU). The Red Zone runs up through the address given there plus 0337; the Yellow Zone starts at 0340, and runs up through 0377.

			In User mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.

	The [[KB11-B CPU]] of the [[PDP-11/70]] has exact same mechanism, as does the [[KD11-K CPU]] of the [[PDP-11/60]].		The [[KB11-B CPU]] of the [[PDP-11/70]] has exact same mechanism, as does the [[KD11-K CPU]] of the [[PDP-11/60]].

Jnc: Jnc moved page PDP-11 stack limit to PDP-11 stacks without leaving a redirect: About to cocolidate stack detaild

2020-06-20T14:40:04Z

Jnc moved page PDP-11 stack limit to PDP-11 stacks without leaving a redirect: About to cocolidate stack detaild

← Older revision		Revision as of 14:40, 20 June 2020
(No difference)

Jnc: copyedits

2020-06-19T12:18:31Z

copyedits

← Older revision		Revision as of 12:18, 19 June 2020
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	Almost all [[PDP-11]] models have some form of [[stack]] overflow protection, which causes a ~~[[Central Processing Unit\|~~CPU]] [[trap]] when the stack overflows. ([[LSI-11 CPUs]] have no overflow detection.) The details of the mechanism vary from model to model; unfortunately, the details are often documented poorly, or not at all.		Almost all [[PDP-11]] [[Central Processing Unit\|CPU]] models have some form of [[stack]] overflow protection, which causes a CPU [[trap]] when the stack overflows. ([[LSI-11 CPUs]] have no overflow detection.) The details of the mechanism vary from model to model; unfortunately, the details are often documented poorly, or not at all.

	==Fixed Limit==		==Fixed Limit==
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	The first PDP-11 CPU, the [[KA11 CPU]] of the [[PDP-11/20]], had a fixed [[address]] limit of 0400; if the stack went below this, a trap occurred after the offending operation ([[instruction]], trap, and probably also [[interrupt]]) was over.		The first PDP-11 CPU, the [[KA11 CPU]] of the [[PDP-11/20]], had a fixed [[address]] limit of 0400; if the stack went below this, a trap occurred after the offending operation ([[instruction]], trap, and probably also [[interrupt]]) was over.

	The [[KD11-B CPU]] of the [[PDP-11/05]] did the exact same thing; as do the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]] (see EK-KD1EA-MM-001, pg. 2-33). [[KDF11 CPUs]] have ~~exact~~ same mechanism (definitely on interrupts, as well; two PS/PC pairs are pushed when this happens).		The [[KD11-B CPU]] of the [[PDP-11/05]] did the exact same thing; as do the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]] (see EK-KD1EA-MM-001, pg. 2-33). [[KDF11 CPUs]] have the same mechanism (definitely on interrupts, as well; two [[Processor Status Word\|PS]]/[[Program Counter\|PC]] pairs, one from the interrupt, and one from the trap, are pushed when this happens).

	[[KDJ11 CPUs]] have a similar mechanism, but although their CPU Error Register has separate Red and Yellow bits (below), interrupts ~~with~~ the SP set below 0400 only set the Yellow bit, and push both ~~interrupt and trap~~ PS/PC pairs; only a fault on the interrupt push causes the Red bit to be set, and then only the interrupt PS/PC are saved (in 0/2; see [[PDP-11 architecture#Stack special-casing\|here]]).		[[KDJ11 CPUs]] have a similar mechanism, but although their CPU Error Register has separate Red and Yellow bits (below), interrupts when the SP is set below 0400 only set the Yellow bit, and push both PS/PC pairs; only a fault on the interrupt push causes the Red bit to be set, and then only the interrupt PS/PC are saved (in 0/2; see [[PDP-11 architecture#Stack special-casing\|here]]).

	==Red/Yellow Zones==		==Red/Yellow Zones and Stack Limit Registers==

	The most complex stack overflow protection mechanism first appeared in the [[KB11-A CPU]] of the [[PDP-11/45]]. In [[~~kernel~~]] mode, it had a 'two-zone' scheme: the 'Yellow Zone' is a 16-[[word]] grace area, in which operations were allowed, but result in a trap after the operation is completed; in the 'Red Zone', all operations are prohibited, and result in an immediate trap.		The most complex stack overflow protection mechanism first appeared in the [[KB11-A CPU]] of the [[PDP-11/45]]. In [[Kernel]] mode, it had a 'two-zone' scheme: the 'Yellow Zone' is a 16-[[word]] grace area, in which operations were allowed, but result in a trap after the operation is completed; in the 'Red Zone', all operations are prohibited, and result in aborting of the operation, and an immediate trap.

	When Red Zone violations occur, the [[Stack Pointer]] is set to 4; the previous ~~[[Program Counter\|~~PC]] and ~~[[Processor Status Word\|~~PS]] are then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses, and use of non-existent memory, result in identical handling.)		When Red Zone violations occur, the [[Stack Pointer]] is set to 4; the previous PC and PS are then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses, and use of non-existent memory, result in identical handling.)

	The [[address]] of the stack limit can be set with the Stack Limit Register [[register]] in the CPU. It is a word register (at 0777774), but the bottom [[byte]] is unused; it is cleared by a reset (e.g. when starting the CPU). The Red Zone runs up through the address given there plus 0337; the Yellow Zone starts at 0340, and runs up through 0377.		The [[address]] of the stack limit can be set with the Stack Limit Register [[register]] in the CPU. It is a word register (at 0777774), but the bottom [[byte]] is unused; it is cleared by a reset (e.g. when starting the CPU). The Red Zone runs up through the address given there plus 0337; the Yellow Zone starts at 0340, and runs up through 0377.

	In [[~~user~~]] mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.		In [[User]] mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.

	The [[~~KD11~~-A CPU]] of the [[PDP-11/40]] has ~~two~~-~~zone stack limitation as above, but at a fixed address~~ of ~~0400; a similar Stack Limit Register is an option,~~ the [[~~KJ11~~-~~A Stack Limit Register~~]]~~. When present, it functions identically to the other two~~.		The [[KB11-B CPU]] of the [[PDP-11/70]] has exact same mechanism, as does the [[KD11-K CPU]] of the [[PDP-11/60]].

	The [[~~KB11~~-B CPU]] of the [[PDP-11/70]] has ~~exact same mechanism~~, as ~~does~~ the [[~~KD11~~-~~K CPU~~]] of the ~~[[PDP-11/60]]~~.		The [[KD11-A CPU]] of the [[PDP-11/40]] has the two-zone stack limitation as above, but at a fixed address of 0400. A similar Stack Limit Register is available as an option, the [[KJ11-A Stack Limit Register]]; when present, it functions identically to the others.

	{{PDP-11}}		{{PDP-11}}

	[[Category: PDP-11s]]		[[Category: PDP-11s]]

Jnc: /60 has SLR and Red/Yellow

2020-06-18T21:49:30Z

/60 has SLR and Red/Yellow

← Older revision		Revision as of 21:49, 18 June 2020
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	The first PDP-11 CPU, the [[KA11 CPU]] of the [[PDP-11/20]], had a fixed [[address]] limit of 0400; if the stack went below this, a trap occurred after the offending operation ([[instruction]], trap, and probably also [[interrupt]]) was over.		The first PDP-11 CPU, the [[KA11 CPU]] of the [[PDP-11/20]], had a fixed [[address]] limit of 0400; if the stack went below this, a trap occurred after the offending operation ([[instruction]], trap, and probably also [[interrupt]]) was over.

	The [[KD11-B CPU]] of the [[PDP-11/05]] did the exact same thing; as do the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]] (see EK-KD1EA-MM-001, pg. 2-33)~~; and the [[KD11-K CPU]] of the [[PDP-11/60]]~~. [[KDF11 CPUs]] have exact same mechanism (definitely on interrupts, as well; two PS/PC pairs are pushed when this happens).		The [[KD11-B CPU]] of the [[PDP-11/05]] did the exact same thing; as do the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]] (see EK-KD1EA-MM-001, pg. 2-33). [[KDF11 CPUs]] have exact same mechanism (definitely on interrupts, as well; two PS/PC pairs are pushed when this happens).

	[[KDJ11 CPUs]] have a similar mechanism, but although their CPU Error Register has separate Red and Yellow bits (below), interrupts with the SP set below 0400 only set the Yellow bit, and push both interrupt and trap PS/PC pairs; only a fault on the interrupt push causes the Red bit to be set, and then only the interrupt PS/PC are saved (in 0/2; see [[PDP-11 architecture#Stack special-casing\|here]]).		[[KDJ11 CPUs]] have a similar mechanism, but although their CPU Error Register has separate Red and Yellow bits (below), interrupts with the SP set below 0400 only set the Yellow bit, and push both interrupt and trap PS/PC pairs; only a fault on the interrupt push causes the Red bit to be set, and then only the interrupt PS/PC are saved (in 0/2; see [[PDP-11 architecture#Stack special-casing\|here]]).
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	In [[user]] mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.		In [[user]] mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.

	~~The [[KB11-B CPU]] of the [[PDP-11/70]] has exact same mechanism.~~ The [[KD11-A CPU]] of the [[PDP-11/40]] has two-zone stack limitation as above, but at a fixed address of 0400; a similar Stack Limit Register is an option, the [[KJ11-A Stack Limit Register]]. When present, it functions identically to the other two.		The [[KD11-A CPU]] of the [[PDP-11/40]] has two-zone stack limitation as above, but at a fixed address of 0400; a similar Stack Limit Register is an option, the [[KJ11-A Stack Limit Register]]. When present, it functions identically to the other two.

			The [[KB11-B CPU]] of the [[PDP-11/70]] has exact same mechanism, as does the [[KD11-K CPU]] of the [[PDP-11/60]].

	{{PDP-11}}		{{PDP-11}}

	[[Category: PDP-11s]]		[[Category: PDP-11s]]

Jnc: no overflow on LSI-11s

2020-06-18T18:34:12Z

no overflow on LSI-11s

← Older revision		Revision as of 18:34, 18 June 2020
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	Almost all [[PDP-11]] models have some form of [[stack]] overflow protection, which causes a [[Central Processing Unit\|CPU]] [[trap]] when the stack overflows. The details of the mechanism vary from model to model; unfortunately, the details are often documented poorly, or not at all.		Almost all [[PDP-11]] models have some form of [[stack]] overflow protection, which causes a [[Central Processing Unit\|CPU]] [[trap]] when the stack overflows. ([[LSI-11 CPUs]] have no overflow detection.) The details of the mechanism vary from model to model; unfortunately, the details are often documented poorly, or not at all.

	==Fixed Limit==		==Fixed Limit==
Line 5:		Line 5:
	The first PDP-11 CPU, the [[KA11 CPU]] of the [[PDP-11/20]], had a fixed [[address]] limit of 0400; if the stack went below this, a trap occurred after the offending operation ([[instruction]], trap, and probably also [[interrupt]]) was over.		The first PDP-11 CPU, the [[KA11 CPU]] of the [[PDP-11/20]], had a fixed [[address]] limit of 0400; if the stack went below this, a trap occurred after the offending operation ([[instruction]], trap, and probably also [[interrupt]]) was over.

	The [[KD11-B CPU]] of the [[PDP-11/05]] did the exact same thing; as do the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]] (see EK-KD1EA-MM-001, pg. 2-33); and the [[KD11-K CPU]] of the [[PDP-11/60]]. [[KDF11 CPUs]] have exact same mechanism (definitely on interrupts, as well).		The [[KD11-B CPU]] of the [[PDP-11/05]] did the exact same thing; as do the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]] (see EK-KD1EA-MM-001, pg. 2-33); and the [[KD11-K CPU]] of the [[PDP-11/60]]. [[KDF11 CPUs]] have exact same mechanism (definitely on interrupts, as well; two PS/PC pairs are pushed when this happens).

	[[KDJ11 CPUs]] have a similar mechanism, but although their CPU Error Register has separate Red and Yellow bits (below), interrupts with the SP set below 0400 only set the Yellow bit, and push both interrupt and trap PS/PC pairs; only a fault on the interrupt push causes the Red bit to be set, and then only the interrupt PS/PC are saved (in 0/2; see [[PDP-11 architecture#Stack special-casing\|here]]).		[[KDJ11 CPUs]] have a similar mechanism, but although their CPU Error Register has separate Red and Yellow bits (below), interrupts with the SP set below 0400 only set the Yellow bit, and push both interrupt and trap PS/PC pairs; only a fault on the interrupt push causes the Red bit to be set, and then only the interrupt PS/PC are saved (in 0/2; see [[PDP-11 architecture#Stack special-casing\|here]]).

← Older revision		Revision as of 18:58, 4 September 2020
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	The [[PDP-11]] makes heavy use of [[stack]]s, for which it has good support via the auto-increment and auto-decrement [[PDP-11 architecture#Addressing modes\|addressing modes]]. However, there are a number of sometimes poorly-documented details of their operation, which ward off potential issues with the main stack (pointed to by R6).		The [[PDP-11]] makes heavy use of [[stack]]s, for which it has good support via the auto-increment and auto-decrement [[PDP-11 architecture#Addressing modes\|addressing modes]]. However, there are a number of sometimes poorly-documented details of their operation, which ward off potential issues with the main stack (pointed to by R6, the main [[Stack Pointer]]).

	* [[Byte]] operations (push and pop) on the R6 stack always adjust the ~~[[Stack Pointer]]~~ by 2, not 1; this to ensure that it always contains a [[word]] [[address]], should an un-expected [[interrupt]] or [[trap]] require it to be used to save the old [[Processor Status Word\|PS]] and [[Program Counter\|PC]].		* [[Byte]] operations (push and pop) on the R6 stack always adjust the SP by 2, not 1; this to ensure that it always contains a [[word]] [[address]], should an un-expected [[interrupt]] or [[trap]] require it to be used to save the old [[Processor Status Word\|PS]] and [[Program Counter\|PC]].

	* On [[Central Processing Unit\|CPU]] models intended for use in [[time-sharing]] systems, which support [[User]] and [[Kernel]] modes, there are separate R6's for the two modes, so that the [[operating system]] can use the latter one for interrupt and trap handling, and thereby guarantee that the user cannot derange R6's contents before it needs to be used.		* On [[Central Processing Unit\|CPU]] models intended for use in [[time-sharing]] systems, which support [[User]] and [[Kernel]] modes, there are separate R6's for the two modes, so that the [[operating system]] can use the latter one for interrupt and trap handling, and thereby guarantee that the user cannot derange R6's contents before it needs to be used.
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	* Almost all models have some form of stack address limitation, which causes a trap when the stack overflows (or tries to). The details vary from model to model; see below for details.		* Almost all models have some form of stack address limitation, which causes a trap when the stack overflows (or tries to). The details vary from model to model; see below for details.

	* When an interrupt or trap occurs, if R6 does contain either an odd (i.e. non-word) address, or an address which does not point to functional [[main memory]], on many models R6 is then bashed to contain 4, after which the old PC and PS are saved in 0 and 2 (respectively); after that, the CPU takes an odd-address/non-existent-memory trap. ([[KDF11 CPUs]] ignore odd stack addresses, and proceed as if the bottom address bit in ~~them~~ is 0. Apparently [[LSI-11 CPUs]] also ignores odd stack addresses.)		* When an interrupt or trap occurs, if R6 does contain either an odd (i.e. non-word) address, or an address which does not point to functional [[main memory]], on many models R6 is then bashed to contain 4, after which the old PC and PS are saved in 0 and 2 (respectively); after that, the CPU takes an odd-address/non-existent-memory trap. ([[KDF11 CPUs]] ignore odd stack addresses, and proceed as if the bottom address bit in their SP is 0. Apparently [[LSI-11 CPUs]] also ignores odd stack addresses.)

	: On the [[KA11 CPU]] ([[PDP-11/20]]), [[KD11-B CPU]] ([[PDP-11/05]]), [[KD11-D CPU]] ([[PDP-11/04]]), [[KD11-E CPU]] ([[PDP-11/34]]), [[KD11-Z CPU]] ([[PDP-11/44]]), and LSI-11 CPUs, a fault during a trap will halt the CPU.		: On the [[KA11 CPU]] ([[PDP-11/20]]), [[KD11-B CPU]] ([[PDP-11/05]]), [[KD11-D CPU]] ([[PDP-11/04]]), [[KD11-E CPU]] ([[PDP-11/34]]), [[KD11-Z CPU]] ([[PDP-11/44]]), and LSI-11 CPUs, a fault during a trap will halt the CPU.
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	==Stack limits==		==Stack limits==

	Almost all PDP-11 CPU models have some form of stack overflow protection, which causes a CPU trap when the stack overflows. ([[LSI-11 CPUs]] have no overflow detection.) The details of the mechanism vary from model to model; unfortunately, the details are often documented poorly, or not at all.		Almost all PDP-11 CPU models have some form of stack overflow protection, which causes a CPU trap when the stack overflows. (LSI-11 CPUs have no overflow detection.) The details of the mechanism vary from model to model; unfortunately, the details are often documented poorly, or not at all.

	===Fixed limit===		===Fixed limit===

	The first PDP-11 CPU, the [[KA11 CPU]] of the [[PDP-11/20]], had a fixed address limit of 0400; if the stack went below this, a trap occurred after the offending operation ([[instruction]], trap, and probably also interrupt) was over.		The first PDP-11 CPU, the KA11 CPU of the PDP-11/20, had a fixed address limit of 0400; if the stack went below this, a trap occurred after the offending operation ([[instruction]], trap, and probably also interrupt) was over.

	The [[KD11-B CPU]] of the [[PDP-11/05]] did the exact same thing; as do the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]] (see EK-KD1EA-MM-001, pg. 2-33). [[KDF11 CPUs]] have the same mechanism (definitely on interrupts, as well; two PS/PC pairs, one from the interrupt, and one from the trap, are pushed when this happens).		The KD11-B CPU of the PDP-11/05 did the exact same thing; as do the KD11-D CPU of the PDP-11/04 and the KD11-E CPU of the PDP-11/34 (see EK-KD1EA-MM-001, pg. 2-33). [[KDF11 CPUs]] have the same mechanism (definitely on interrupts, as well; two PS/PC pairs, one from the interrupt, and one from the trap, are pushed when this happens).

	[[KDJ11 CPUs]] have a similar mechanism, but although their CPU Error Register has separate Red and Yellow bits (below), interrupts when the SP is set below 0400 only set the Yellow bit, and push both PS/PC pairs. Only a fault on the interrupt push causes the Red bit to be set, and then only the interrupt PS/PC are saved (in 0/2; see above for more).		[[KDJ11 CPUs]] have a similar mechanism, but although their CPU Error Register has separate Red and Yellow bits (below), interrupts when the SP is set below 0400 only set the Yellow bit, and push both PS/PC pairs. Only a fault on the interrupt push causes the Red bit to be set, and then only the interrupt PS/PC are saved (in 0/2; see above for more).
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	When Red Zone violations occur, the SP is set to 4; the previous PC and PS are then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses, and use of non-existent memory, result in identical handling.)		When Red Zone violations occur, the SP is set to 4; the previous PC and PS are then saved in locations 0 and 2 by the resulting trap. (Odd stack addresses, and use of non-existent memory, result in identical handling.)

	The address of the stack limit can be set with the Stack Limit Register ~~[[register]]~~ in the CPU. It is a word register (at 0777774), but the bottom byte is unused; it is cleared by a reset (e.g. when starting the CPU). The Red Zone runs up through the address given there plus 0337; the Yellow Zone starts at 0340, and runs up through 0377.		The address of the stack limit can be set with the Stack Limit Register in the CPU. It is a word [[register]] (at 0777774), but the bottom byte is unused; it is cleared by a reset (e.g. when starting the CPU). The Red Zone runs up through the address given there plus 0337; the Yellow Zone starts at 0340, and runs up through 0377.

	In User mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.		In User mode, there is a fixed Stack Overflow Boundary at 0400; attempts to write below that address cause an immediate trap.