PDP-8/L - Revision history

Jnc: Reverted edits by Larsbrinkhoff (talk) to last revision by ForOldHack

2023-07-14T12:11:37Z

Reverted edits by Larsbrinkhoff (talk) to last revision by ForOldHack

Larsbrinkhoff: 12-bit cat.

2023-07-11T11:46:43Z

12-bit cat.

ForOldHack: /* External links */

2022-08-14T23:19:43Z

‎External links

Jnc: /* External links */ typo

2021-05-16T16:29:36Z

‎External links: typo

Jnc: MC-8/L differs from MC-8/I

2021-05-16T01:25:02Z

MC-8/L differs from MC-8/I

Jnc: +links, Ext links

2021-05-16T01:01:20Z

+links, Ext links

Jnc: +img

2021-01-09T14:03:00Z

+img

Jnc: fix link

2019-11-22T20:29:05Z

fix link

Jnc: +cat

2018-09-07T13:03:28Z

+cat

Jnc: An acceptable start...

2018-09-03T21:16:11Z

An acceptable start...

New page

{{Infobox Machine
| name = PDP-8/L

| year introduced = 1968
| form factor = [[minicomputer]]
| word size = 12
| physical address = 8KW (requires optional MC-8/L)
| virtual address = 4KW
| logic type = [[Transistor-transistor logic|TTL]]
| design type = [[clock]]ed random [[logic]]
| clock speed = 312KHz
| memory speed = 1.6 µseconds
| bus arch = positive logic I/O bus
| memory mgmt = none
| operating system = [[TSS/8]]
| predecessor = [[PDP-8/I]]
| successor = [[PDP-8/E]]
}}

The '''PDP-8/L''' was a effectively a cost-reduced version of the [[PDP-8/I]] in the [[PDP-8]] line; it apparently had the same [[Central Processing Unit|CPU]] as the -8/I.

The primary differences between the two are:

* The -8/L was slightly slower
* The -8/L used a positive I/0 bus, not negative
* The -8/L was not pre-wired for a number of devices
* The -8/L could not accomodate the Extended Arithmetic Element
* The -8/L supported a maximum of 8KW of [[main memory]]

Options for the -8/L included:

* DW08-A Negative I/O Bus Interface, to allow use of older PDP-8 devices
* MC-8/L Memory Extension Control, which was needed to support more than 4K [[word]]s of memory
* MP-8/L Memory Parity

It could perform an addition to the [[accumulator]] in 3.2 µseconds, and a subtraction in 6.4 µseconds.

{{Nav PDP-8}}

← Older revision		Revision as of 12:11, 14 July 2023
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	[[Category: PDP-8s]]		[[Category: PDP-8s]]
−	~~[[Category: 12-bit Computers]]~~

← Older revision		Revision as of 11:46, 11 July 2023
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	[[Category: PDP-8s]]		[[Category: PDP-8s]]
		+	[[Category: 12-bit Computers]]

@@ Line 45: / Line 45: @@
 * [http://www.bitsavers.org/pdf/dec/pdp8/pdp8l PDP-8/L] - Original PDP-8/L documents
+* [https://commons.princeton.edu/motorcycledesign/wp-content/uploads/sites/70/2018/07/DEC-PDP-8L-Maintenance-Manual-Volume-1.pdf PDP-8/L-Maintenance-Manual-Volume-1] - Maintenance manual.
 {{Nav PDP-8}}
 [[Category: PDP-8s]]

@@ Line 44: / Line 44: @@
 ==External links==
-* [http://www.bitsavers.org/pdf/dec/pdp8l PDP-8/L] - Original PDP-8/L documents
+* [http://www.bitsavers.org/pdf/dec/pdp8/pdp8l PDP-8/L] - Original PDP-8/L documents
 {{Nav PDP-8}}
 [[Category: PDP-8s]]

@@ Line 37: / Line 37: @@
 * MC-8/L Memory Extension Control, [[bank switching]] needed to support more than 4K [[word]]s of memory
 * MP-8/L Memory [[Parity]]
 It could perform an addition to the [[accumulator]] in 3.2 µseconds, and a subtraction in 6.4 µseconds.

@@ Line 29: / Line 29: @@
 * The -8/L used a positive I/0 bus, not negative
 * The -8/L was not pre-wired for a number of devices
-* The -8/L could not accomodate the Extended Arithmetic Element
+* The -8/L could not accomodate the [[Extended Arithmetic Element]]
 * The -8/L supported a maximum of 8KW of [[main memory]]
@@ Line 35: / Line 35: @@
 * DW08-A Negative I/O Bus Interface, to allow use of older PDP-8 devices
-* MC-8/L Memory Extension Control, which was needed to support more than 4K [[word]]s of memory
+* MC-8/L Memory Extension Control, [[bank switching]] needed to support more than 4K [[word]]s of memory
-* MP-8/L Memory Parity
+* MP-8/L Memory [[Parity]]
 It could perform an addition to the [[accumulator]] in 3.2 µseconds, and a subtraction in 6.4 µseconds.
 {{Nav PDP-8}}
 [[Category: PDP-8s]]

@@ Line 1: / Line 1: @@
 {{Infobox Machine
 | name = PDP-8/L
 <!--
 | ram = Maximum of 32 kwords in eight 4 kword banks
 -->

@@ Line 22: / Line 22: @@
 }}
-The '''PDP-8/L''' was a effectively a cost-reduced version of the [[PDP-8/I]] in the [[PDP-8]] line; it apparently had the same [[Central Processing Unit|CPU]] as the -8/I.
+The '''PDP-8/L''' was a effectively a cost-reduced version of the [[PDP-8/I]] in the [[PDP-8 family|PDP-8]] line; it apparently had the same [[Central Processing Unit|CPU]] as the -8/I.
 The primary differences between the two are:

← Older revision		Revision as of 13:03, 7 September 2018
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	{{Nav PDP-8}}		{{Nav PDP-8}}
		+
		+	[[Category: PDP-8s]]