PDP-8/S - Revision history

Jnc: Reverted edits by Larsbrinkhoff (talk) to last revision by Jnc

2023-07-14T12:10:03Z

Reverted edits by Larsbrinkhoff (talk) to last revision by Jnc

Larsbrinkhoff: 12-bit cat.

2023-07-11T11:47:58Z

12-bit cat.

Jnc: +img

2021-01-08T16:07:11Z

+img

Jnc: give cycle time in time units

2019-08-25T12:03:29Z

give cycle time in time units

Jnc: Secondary source wrong - see Talk page

2019-08-19T13:40:53Z

Secondary source wrong - see Talk page

Nczempin: see "Computer Structures: Readings and Examples", page 120: "A PDP-S/S is one-fifteenth of a PDP-8 at one-half the cost. ...even though the same 2-megahertz logic clock is used in both cases."

2019-08-18T17:35:59Z

see "Computer Structures: Readings and Examples", page 120: "A PDP-S/S is one-fifteenth of a PDP-8 at one-half the cost. ...even though the same 2-megahertz logic clock is used in both cases."

Jnc: Add image of front panel inlay

2018-11-13T16:43:50Z

Add image of front panel inlay

Jnc: Created page with "{{Infobox Machine | name = PDP-8/S | manufacturer = DEC | form factor = minicomputer | word size = 12 bits | year introduced = 1967 | yea..."

2018-09-06T01:33:07Z

Created page with "{{Infobox Machine | name = PDP-8/S | manufacturer = DEC | form factor = minicomputer | word size = 12 bits | year introduced = 1967 | yea..."

New page

{{Infobox Machine
| name = PDP-8/S
| manufacturer = [[Digital Equipment Corporation|DEC]]
| form factor = [[minicomputer]]
| word size = 12 bits
| year introduced = 1967
| year discontinued = 1970
| architecture = [[PDP-8 architecture|PDP-8]]
| physical address = 32KW (requires optional MC8S)
| virtual address = 4KW
| design type = [[clock]]ed random [[logic]]
| clock speed = 100KHz
| memory speed = 8 μseconds
| memory mgmt = bank select
| logic type = [[diode transistor logic|DTL]]
| bus arch = Negative I/O Bus
| predecessor = [[PDP-8]]
| successor = [[PDP-8/L]]

}}

The '''PDP-8/S''' was [[Digital Equipment Corporation|DEC]]'s attempt to produce a 'cheaper' [[PDP-8]]. It was a [[serial computer|serial]] implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued.

The PDP-8 was constructed with discrete [[transistor]]s, packaged into DEC's [[FLIP CHIP]] technology. It could perform an addition to the [[accumulator]] in 64 μseconds. It had [[parity]] on the [[main memory]] as standard, not optional.

==Options==

Options included:

* DB8S Data Break, needed for data break on the I/O bus
* MC8S Memory Extension Control, which was needed to support more than 4K [[word]]s of memory
* MM8S Memory Module
* ME8S Memory Extension, holds two MM8S

{{Nav PDP-8}}

[[Category: PDP-8s]]

← Older revision		Revision as of 12:10, 14 July 2023
Line 50:		Line 50:

	[[Category: PDP-8s]]		[[Category: PDP-8s]]
−	~~[[Category: 12-bit Computers]]~~

← Older revision		Revision as of 11:47, 11 July 2023
Line 50:		Line 50:

	[[Category: PDP-8s]]		[[Category: PDP-8s]]
		+	[[Category: 12-bit Computers]]

@@ Line 12: / Line 12: @@
 | virtual address = 4k words
 | design type = [[clock]]ed random [[logic]]
-| clock speed = 2 MHz
+| clock speed = 1.333Mhz (bit) / 95kHz (word)
 | memory speed = 8 μseconds
 | memory mgmt = bank select
@@ Line 30: / Line 30: @@
 }}
-The '''PDP-8/S''' was [[Digital Equipment Corporation|DEC]]'s attempt to produce a 'cheaper' [[PDP-8]]. It was a [[serial computer|serial]] implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued.
+The '''PDP-8/S''' was [[Digital Equipment Corporation|DEC]]'s attempt to produce a 'cheaper' [[PDP-8 family|PDP-8]]. It was a [[serial computer|serial]] implementation, which reduced the part count somewhat, but resulted in an incredibly slow machine, compared to the rest of the line. It was soon discontinued.
 The PDP-8 was constructed with discrete [[transistor]]s, packaged into DEC's [[FLIP CHIP]] technology. It could perform an addition to the [[accumulator]] in 64 μseconds. It had [[parity]] on the [[main memory]] as standard, not optional.

@@ Line 42: / Line 42: @@
 * MM8S Memory Module
 * ME8S Memory Extension, holds two MM8S
 {{Nav PDP-8}}
 [[Category: PDP-8s]]

@@ Line 12: / Line 12: @@
 | virtual address = 4k words
 | design type = [[clock]]ed random [[logic]]
-| clock speed = 1.333Mhz (bit) / 95kHz (word)
+| clock speed = 1.333Mhz (per bit)
 | memory speed = 8 μseconds
 | memory mgmt = bank select
@@ Line 20: / Line 21: @@
 | successor = [[PDP-8/L]]
 <!--
 | year announced      =
 | year design started =
@@ Line 26: / Line 26: @@
 | cpu                 =
 | operating system    =
-| price = US$18,500
+| price = US$
 -->
 }}

@@ Line 9: / Line 9: @@
 | year discontinued = 1970
 | architecture = [[PDP-8 architecture|PDP-8]]
-| physical address = 32KW (requires optional MC8S)
+| physical address = 32k words (requires optional MC8S)
-| virtual address = 4KW
+| virtual address = 4k words
 | design type = [[clock]]ed random [[logic]]
-| clock speed = 100KHz
+| clock speed = 2 MHz
 | memory speed = 8 μseconds
 | memory mgmt = bank select
@@ Line 39: / Line 39: @@
 * DB8S Data Break, needed for data break on the I/O bus
-* MC8S Memory Extension Control, which was needed to support more than 4K [[word]]s of memory
+* MC8S Memory Extension Control, which was needed to support more than 4k [[word]]s of memory
 * MM8S Memory Module
 * ME8S Memory Extension, holds two MM8S

@@ Line 1: / Line 1: @@
 {{Infobox Machine
 | name = PDP-8/S
 | manufacturer = [[Digital Equipment Corporation|DEC]]
@@ Line 18: / Line 20: @@
 | successor = [[PDP-8/L]]
 <!--
-| image = PDP-8.jpg
 | year announced      =
 | year design started =