PDP-8 architecture - Revision history

Jnc: /* External links */ +Bitsavers

2022-11-29T17:34:21Z

‎External links: +Bitsavers

Jnc: /* Input/Output */ +link

2022-05-20T11:26:48Z

‎Input/Output: +link

Jnc: Use DEC term, add some links

2021-09-19T13:38:49Z

Use DEC term, add some links

Jnc: /* External links */ standard naming system

2021-05-22T18:40:32Z

‎External links: standard naming system

Jnc: consistent nav bar naming

2021-05-18T21:57:53Z

consistent nav bar naming

Jnc: Add auto-indexing; link ne Memory Expansion unit page

2021-05-18T20:26:03Z

Add auto-indexing; link ne Memory Expansion unit page

Jnc: Better organization; show basic inst formet

2021-05-17T14:27:52Z

Better organization; show basic inst formet

Show changes

Jnc: +ext link

2021-03-03T00:57:13Z

+ext link

Jnc: +See also

2018-09-07T13:15:37Z

+See also

Jnc: /* Input/Output */ Mention address from jumpers

2018-09-05T03:46:53Z

‎Input/Output: Mention address from jumpers

← Older revision		Revision as of 17:34, 29 November 2022
Line 246:		Line 246:
	==External links==		==External links==

		+	* [http://www.bitsavers.org/pdf/dec/pdp8/ PDP8] - documentation at [[Bitsavers]]
	* [http://www.quadibloc.com/comp/cp0306.htm Another Real Machine: The DEC PDP-8]		* [http://www.quadibloc.com/comp/cp0306.htm Another Real Machine: The DEC PDP-8]

@@ Line 130: / Line 130: @@
 All supported [[Direct Memory Access|DMA]], called "data break" in the PDP-8's. There were two types.
-In one, "three-cycle data break", the buffer address and word count were kept in main memory (at an [[address]] usually specified by [[jumper]]s on the device). This required the assistance of the processor, placing the processor in charge of maintaining the DMA address and word count. This moved some of common logic (needed to implement the I/O device) from each I/O device into one common copy of the logic within the processor, reducing the device complexity (and thus cost). In three successive memory cycles, the processor would update the word count, update the transfer address, and finally store or retrieve the actual I/O data word.
+In one, "[[three cycle data break]]", the buffer address and word count were kept in main memory (at an [[address]] usually specified by [[jumper]]s on the device). This required the assistance of the processor, placing the processor in charge of maintaining the DMA address and word count. This moved some of common logic (needed to implement the I/O device) from each I/O device into one common copy of the logic within the processor, reducing the device complexity (and thus cost). In three successive memory cycles, the processor would update the word count, update the transfer address, and finally store or retrieve the actual I/O data word.
-The other, "single-cycle data break", moved back to the individual I/O devices all the responsibility for maintaining the word count and transfer address (in registers in the device); this effectively tripled the DMA transfer rate because only the target data needed to be transferred to/from the main memory.
+The other, "single cycle data break", moved back to the individual I/O devices all the responsibility for maintaining the word count and transfer address (in registers in the device); this effectively tripled the DMA transfer rate because only the target data needed to be transferred to/from the main memory.
 == Programming Facilities ==

@@ Line 5: / Line 5: @@
 The PDP-8's basic configuration had a [[main memory]] (all [[core memory]], in the early models) of 4,096 twelve-[[bit]] [[word]]s (that is, 4K words, equivalent to 6 kilobytes). In most models, that was expandable to 32,768 words (32K words / 48 KB), which were controlled by optional additional [[hardware]].
-At its inception, the PDP-8 had only eight [[instruction]]s and two [[register]]s (a 12-bit [[accumulator]], AC; and a single-bit "link register", L). The first model used a magnetic core memory system that operated at a cycle time of 1.5 microseconds, so that a typical two-cycle (Fetch, Execute) memory-reference instruction ran at a speed of 0.333 MIPS.
+At its inception, the PDP-8 had only eight [[instruction]]s and two [[register]]s (a 12-bit [[accumulator]], AC; and a single-bit "link register", L). The first model used a magnetic core memory system that operated at a cycle time of 1.5 microseconds, so that a typical two-cycle ([[Fetch]], Execute) memory-reference instruction ran at a speed of 0.333 MIPS.
-Later models added a second register (the "MQ" Multiplier/Quotient Register), optional actual hardware multiply and divide instructions, and faster operation. The last models also supported optional hardware [[floating point]].
+Later models added a second register (the "MQ" Multiplier/Quotient Register), optional actual [[hardware]] multiply and divide instructions, and faster operation. The last models also supported optional hardware [[floating point]].
 == Instruction Set ==
@@ Line 30: / Line 30: @@
 :010 - ISZ - Increment the memory operand and Skip next instruction if result is Zero.
 :011 - DCA - Deposit AC into the memory operand and Clear AC.
-:100 - JMS - JuMp to Subroutine (storing return address in first word of subroutine!).
+:100 - JMS - [[jump|JuMp]] to [[Subroutine]] (storing return address in first word of subroutine!).
 :101 - JMP - JuMP.
 :110 - IOT - Input/Output Transfer.
 :111 - OPR - microcoded OPeRations (on/using the accumulator, link, and MQ registers).
-A wide variety of operations are available through the OPR 'microcoded' instructions including most of the [[conditional branch]] (skip) instructions. In general, the operations within each Group can be combined by OR'ing the bit patterns for the desired operations into a single instruction.
+A wide variety of operations are available through the OPR 'microcoded' instructions, including most of the [[conditional branch]] (skip) instructions. In general, the operations within each Group can be combined by OR'ing the bit patterns for the desired operations into a single instruction.
 === Group 1 "operate" instruction operations ===
 :CLA - clear AC
 :CLL - clear the L bit
@@ Line 55: / Line 56: @@
 === Group 2 "operate" instruction operations ===
 :SMA - skip on AC < 0 (or group)
 :SZA - skip on AC = 0 (or group)
@@ Line 95: / Line 97: @@
 == Memory Control ==
-The basic PDP-8 instruction set could only address 4,096 12-bit words of memory.  While this was somewhat adequate for very small programs, once the price of memory came down a bit, it was desirable to increase the amount of addressable memory.  The way this was done was, depending on your point of view, very clever or a huge kludge; [[bank switching]], supported by optional hardware, was added. This approach in many ways resembles the solution chosen for the later [[Intel 8086]] which added "segments" to a 16 bit address to create a 20 bit address, which also created problems, but was cheaper than re-engineering an entirely new design.
+The basic PDP-8 [[instruction set]] could only address 4,096 12-bit words of memory.  While this was somewhat adequate for very small programs, once the price of memory came down a bit, it was desirable to increase the amount of addressable memory.  The way this was done was, depending on your point of view, very clever or a huge kludge; [[bank switching]], supported by optional hardware, was added. This approach in many ways resembles the solution chosen for the later [[Intel 8086]] which added "[[segment]]s" to a 16 bit address to create a 20 bit address, which also created problems, but was cheaper than re-engineering an entirely new instruction set.
 Ideally one would expand the size of addresses, but this would require major rework of the architecture and likely make all existing [[program]]s not work.  Instead the designers thought of a way of extending the address space while allowing full compatibility with existing programs.
-This was done by adding a [[PDP-8 Memory Expansion units‎|Memory Extension Controller]].  This controller expanded the addressable memory by 4KW blocks of memory; each 4KW block of memory was called a "field".  This may sound like not too much memory, but core memory in those days cost about 50 cents a word, so a full 32K complement of memory would equal the cost of the CPU.
+This was done by adding a [[PDP-8 Memory Extension units‎|Memory Extension Controller]].  This controller expanded the addressable memory by 4KW blocks of memory; each 4KW block of memory was called a "field".  This may sound like not too much memory, but core memory in those days cost about 50 cents a word, so a full 32K complement of memory would equal the cost of the CPU.
 The current field was controlled by two three-bit registers: the DF (Data Field) and the IF (Instruction Field).  These registers were grafted onto all memory accesses. For accesses from the CPU for instructions, the IF field register was grafted onto the memory request address. For data accesses with indirection, the DF register was used. With this clever combination, a program running in one field could access data in the same field by direct addressing, or data in another field with indirect addressing.
@@ Line 111: / Line 113: @@
 On the PDP-8/E and later models the Extended Memory Controller had a few minor enhancements which made machine virtualization possible. By making all I/O instructions cause an interrupt, a [[virtual machine]] manager could do memory mapping, for instance mapping data or instruction fields on the fly. It could also redirect I/O to different devices. A rather sophisticated feature for a machine with only eight basic instructions!
-One glitch in the virtualization was that there was one bit of machine state that was not possible to restore. When executing a CIF instruction, the change did not take place immediately, but was delayed until the next jump or call. This state was not readable or settable, so there was no way for the virtualizer to simulate a CIF and set the proper machine state. This required the virtualizer to have a complete PDP-8 code simulator in it (not that hard  a task for an 8-instruction machine). Whenever a CIF instruction trapped to the virtualizer, it had to emulate the instructions between the CIF and the next JMP or JMS. Fortunately most programmers did not insert any instructions between the CIF and JMS, so the emulator did not slow things very much.  Still, it's an interesting example of how just one missing bit can lead to requiring much additional code.
+One glitch in the virtualization was that there was one bit of machine state that was not possible to restore. When executing a CIF instruction, the change did not take place immediately, but was delayed until the next jump or [[call]]. This state was not readable or settable, so there was no way for the virtualizer to simulate a CIF and set the proper machine state. This required the virtualizer to have a complete PDP-8 code simulator in it (not that hard  a task for an 8-instruction machine). Whenever a CIF instruction trapped to the virtualizer, it had to emulate the instructions between the CIF and the next JMP or JMS. Fortunately most programmers did not insert any instructions between the CIF and JMS, so the emulator did not slow things very much.  Still, it's an interesting example of how just one missing bit can lead to requiring much additional code.
 By the time of the [[PDP-8/A]], memory prices had come down enough so 32K was not a huge budgetary item and more memory was desireable. The 8/A added a new set of instructions for handling more than eight fields of memory.  Particularly useful were new instructions that took the field number from the AC instead of requiring the field number to be hard-coded into the instruction. Unfortunately by this time the PDP-8 was in its decline, so very little standard system software was modified to take advantage of these new instructions and extra memory.
@@ Line 117: / Line 119: @@
 == Input/Output ==
-The I/O systems underwent huge changes during the PDP-8 era. Early PDP-8 models used a front panel interface, a [[paper tape]] reader and a teletype printer with an optional paper tape punch. Over time I/O systems such as [[magnetic tape]], RS-232 and current loop dumb terminals, [[punched card]] readers, and [[fixed-head disk]]s were added. Toward the end of the PDP-8 era, [[floppy disk]]s and moving-head cartridge [[disk]] drives were popular I/O devices. Modern enthusiasts have created standard PC style IDE hard disk adapters for real and simulated PDP-8 computers.
+The I/O systems underwent huge changes during the PDP-8 era. Early PDP-8 models used a [[front panel]] interface, a [[paper tape]] reader and a teletype printer with an optional paper tape punch. Over time I/O systems such as [[magnetic tape]], RS-232 and current loop dumb terminals, [[punched card]] readers, and [[fixed-head disk]]s were added. Toward the end of the PDP-8 era, [[floppy disk]]s and moving-head cartridge [[disk]] drives were popular I/O devices. Modern enthusiasts have created standard PC style IDE hard disk adapters for real and simulated PDP-8 computers.
 I/O was supported through several different methods, which changed over time and various PDP-8 models:

@@ Line 246: / Line 246: @@
 * [http://www.quadibloc.com/comp/cp0306.htm Another Real Machine: The DEC PDP-8]
-{{PDP-8}}
+{{Nav PDP-8}}
-{{DEC}}
+{{Nav DEC}}
 [[Category: PDP-8s]]
 [[Category: DEC Architectures]]

@@ Line 246: / Line 246: @@
 * [http://www.quadibloc.com/comp/cp0306.htm Another Real Machine: The DEC PDP-8]
-{{Nav PDP-8}}
+{{PDP-8}}
 {{DEC}}
 [[Category: PDP-8s]]
 [[Category: DEC Architectures]]

@@ Line 7: / Line 7: @@
 At its inception, the PDP-8 had only eight [[instruction]]s and two [[register]]s (a 12-bit [[accumulator]], AC; and a single-bit "link register", L). The first model used a magnetic core memory system that operated at a cycle time of 1.5 microseconds, so that a typical two-cycle (Fetch, Execute) memory-reference instruction ran at a speed of 0.333 MIPS.
-Later models added a second register (the "MQ" Multiplier/Quotient Register), optional actual hardware multiply and divide instruction options, and faster operation. The last models also supported optional hardware [[floating point]].
+Later models added a second register (the "MQ" Multiplier/Quotient Register), optional actual hardware multiply and divide instructions, and faster operation. The last models also supported optional hardware [[floating point]].
 == Instruction Set ==
@@ Line 16: / Line 16: @@
 {{12bitoctal-bitout}}
-To explain this, a special term is used with PDP-8 main memory: 'page'. This has nothing to do with the now-ubiquitous 'pages' of [[virtual memory]]; rather, it is has to do with the fact that PDP-8 instructions are 12 bits wide (the size of its words), as is its [[address space]]. It is thus impossible to fully address the memory from a PDP-8 instruction; rather, PDP-8 instructions contain only a 7-bit offset field, the 'address' field. The visible main memory is divided into 32 (040) 'pages', each 128 (0200) words long. Another bit in each instruction, the 'memory page' bit, indicates whether the offset is in the current page (if '1'), or page 0 (if '0'). To refer to a word in another page, it was necessary to use an [[indirect]] reference (controlled by another bit in the instruction) through an address stored in either of the two directly accessible pages.
+To explain this, a special term is used with PDP-8 main memory: 'page'. This has nothing to do with the now-ubiquitous 'pages' of [[virtual memory]]; rather, it is has to do with the fact that PDP-8 instructions are 12 bits wide (the size of its words), as is its [[address space]]. It is thus impossible to fully [[address]] all the memory from a PDP-8 instruction; rather, PDP-8 instructions contain only a 7-bit offset field, the 'address' field. The visible main memory is divided into 32 (040) 'pages', each 128 (0200) words long. Another bit in each instruction, the 'memory page' bit, indicates whether the offset is in the current page (if '1'), or page 0 (if '0').
 === Basic Instructions ===
@@ Line 90: / Line 94: @@
 == Memory Control ==
-Ideally one would expand the size of [[address]]es, but this would require major rework of the architecture and likely make all existing [[program]]s not work.  Instead the designers thought of a way of extending the [[address space]] while allowing full compatibility with existing programs.
+The basic PDP-8 instruction set could only address 4,096 12-bit words of memory.  While this was somewhat adequate for very small programs, once the price of memory came down a bit, it was desirable to increase the amount of addressable memory.  The way this was done was, depending on your point of view, very clever or a huge kludge; [[bank switching]], supported by optional hardware, was added. This approach in many ways resembles the solution chosen for the later [[Intel 8086]] which added "segments" to a 16 bit address to create a 20 bit address, which also created problems, but was cheaper than re-engineering an entirely new design.
-This was done by adding an "Memory Extension Controller".  This controller expanded the addressable memory by a factor of 8, three bits, to a total of 32,768 words. Each 4K of memory was called a "field".  This may sound like not too much memory, but core memory in those days cost about 50 cents a word, so a full 32K complement of memory would equal the cost of the CPU.
+Ideally one would expand the size of addresses, but this would require major rework of the architecture and likely make all existing [[program]]s not work.  Instead the designers thought of a way of extending the address space while allowing full compatibility with existing programs.
-The current field was controlled by two three-bit registers: the DF (Data Field) and the IF (Instruction Field).  These registers were grafted onto all memory accesses.  For accesses from the CPU for instructions, the IF field register was grafted onto the memory request address. For data accesses with indirection, the DF register was used.  With this clever combination, a program running in one field could access data in the same field by direct addressing, or data in another field with indirect addressing.
+This was done by adding a [[PDP-8 Memory Expansion units‎|Memory Extension Controller]].  This controller expanded the addressable memory by 4KW blocks of memory; each 4KW block of memory was called a "field".  This may sound like not too much memory, but core memory in those days cost about 50 cents a word, so a full 32K complement of memory would equal the cost of the CPU.
 The DF and IF registers were controlled by a set of pseudo-IO instructions. The 6200 through 6277 range of IO instructions were reserved for the extended memory controller. The 62X1 instuction (CDF, Change Data Field) would set the data field to X. Similarly 62X2, CIF, set the instruction field, 62X3 set both. The instruction field change did not take effect until after the completion of the next JMP or JMS instruction, to avoid wild changes of execution. The DF and IF registers were part of the machine state, so there were also instructions for getting and setting these registers, usually used for saving the machine state on an interrupt.
@@ Line 240: / Line 245: @@
 * [http://www.quadibloc.com/comp/cp0306.htm Another Real Machine: The DEC PDP-8]
 [[Category: PDP-8s]]
 [[Category: DEC Architectures]]

@@ Line 1: / Line 1: @@
 {{wp-orig}}
-The [[PDP-8]] is a 12-bit [[architecture]].  The PDP-8's basic configuration had a [[main memory]] of 4,096 twelve-[[bit]] [[word]]s (that is, 4K words, equivalent to 6 kilobytes), expandable to 32,768 words (32K words / 48 KB) which were controlled by the IOT [[instruction]] and additional [[hardware]].
+The [[PDP-8 family|PDP-8]] is a 12-bit [[architecture]].  The PDP-8's basic configuration had a [[main memory]] of 4,096 twelve-[[bit]] [[word]]s (that is, 4K words, equivalent to 6 kilobytes), expandable to 32,768 words (32K words / 48 KB) which were controlled by the IOT [[instruction]] and additional [[hardware]].
-At its inception, the PDP-8 had only eight instructions and two [[register]]s (a 12-bit [[accumulator]], AC, and a single-bit "link register", L). The machine used a magnetic [[core memory]] system that operated at a cycle time of 1.5 microseconds, so that a typical two-cycle (Fetch, Execute) memory-reference instruction ran at a speed of 0.333 MIPS.
+At its inception, the PDP-8 had only eight instructions and two [[register]]s (a 12-bit [[accumulator]], AC; and a single-bit "link register", L). The machine used a magnetic [[core memory]] system that operated at a cycle time of 1.5 microseconds, so that a typical two-cycle (Fetch, Execute) memory-reference instruction ran at a speed of 0.333 MIPS.
 Later machines added a second register (the "MQ" Multiplier/Quotient Register), actual hardware multiply and divide instruction options, and faster operation. The last versions also supportd hardware [[floating point]].
@@ Line 223: / Line 223: @@
 The stark simplicity of the architecture and the instruction set make the PDP-8 valuable as a mental model for teaching the rudiments of architecture and of assembly language to beginners. A complete lesson, requiring no lecture notes, can be delivered in 15 minutes by anyone who ever programmed in PDP-8 assembler. The same cannot be said for most of the more recent architectures.
 [[Category: PDP-8s]]
 [[Category: DEC Architectures]]