PDP-9 control memory - Revision history

Larsbrinkhoff: Even more clarity.

2023-08-13T07:37:31Z

Even more clarity.

Larsbrinkhoff: Moved the wiring matrix up, so that the next header "Decoded..." makes sense in referring to the matrix.

2023-08-13T07:36:51Z

Moved the wiring matrix up, so that the next header "Decoded..." makes sense in referring to the matrix.

Larsbrinkhoff: /* Explanation */ XCT/JMP/EAE/IOT/OPR jumps from 24 directly to 60-77.

2023-07-27T10:18:10Z

‎Explanation: XCT/JMP/EAE/IOT/OPR jumps from 24 directly to 60-77.

Larsbrinkhoff: /* CMA modification */ More about switches affecting CMA.

2023-07-25T05:52:21Z

‎CMA modification: More about switches affecting CMA.

Larsbrinkhoff: /* Explanation */ There can only be one level of indirection.

2023-07-23T17:14:57Z

‎Explanation: There can only be one level of indirection.

Jnc: Not really very stubby any more; slightly improve layout; +cat

2023-07-23T15:25:23Z

Not really very stubby any more; slightly improve layout; +cat

Larsbrinkhoff: /* Explanation */ Also read-in.

2023-07-23T09:10:08Z

‎Explanation: Also read-in.

Larsbrinkhoff: /* Explanation */ Map out the control memory regions.

2023-07-23T09:09:11Z

‎Explanation: Map out the control memory regions.

Larsbrinkhoff: /* Explanation */ Flesh out a little more.

2023-07-23T09:03:16Z

‎Explanation: Flesh out a little more.

Larsbrinkhoff: /* Explanation */ Typos.

2023-07-23T08:44:06Z

‎Explanation: Typos.

@@ Line 105: / Line 105: @@
 <br clear=all>
-===Decoded to binary and symbolic form===
+===Matrix decoded to binary and symbolic form===
 {| class="wikitable"
 ! Address || Process word bits || Symbolic description

@@ Line 99: / Line 99: @@
 * In address range 60-77, the lower four bits come from the upper four bits of the instruction register.  Hence each process word in this range implements one of the 16 instructions.
 ===Decoded to binary and symbolic form===
@@ Line 263: / Line 268: @@
 Each process word in the region 60-77 implements the execution phase of one of the 16 PDP-9 instructions.
 [[Category: DEC Processors]]

@@ Line 248: / Line 248: @@
 * 24: TI SM CMA/30<br>TI makes a check for indirect addressing.  SM starts a new memory access to retrieve the instruction operand.
 * A new memory cycle starts, reading MB into MA.
-* At this point, CMA 30 may be "boosted" by random logic.  If there's indirect addressing, processing continues at CMA 31.  If the IR holds a CAL, DAC, JMS, or DZM instruction, processing continues at 32.  Otherwise, proceed to the unboosted address 30.
+* At this point, CMA 30 may be "boosted" by random logic.  If there's indirect addressing, processing continues at CMA 31.  If the IR holds a CAL, DAC, JMS, or DZM instruction, processing continues at 32.  For XCT, JMP, EAE, IOT, or OPR without indirect addressing, the CMA is short-circuited directly to 7x and dispatching to the 60-77 region.  Otherwise, proceed to the unboosted address 30.
 ** 30: DEI CJIT CMA/60<br>DEI ensures MBI and SAO are set to retrieve the memory operand.  CJIT activates a check for ISZ with operand 0, and increments the PC if so.  The next CMA is "boosted" by putting the instruction opcode in the lower four bits, thus dispatching to CMA 60-77.
 ** 31: DEI CMA/24<br>DEI clears the indirect addressing bit in IR4.  The memory cycle read phase has put the indirect address in MB.  Processing loops back to CMA 24 to start a new memory cycle using MB as the address.  There can't be any more loop since IR4 was cleared.

@@ Line 81: / Line 81: @@
 ! Value || Switch
 |-
-| 1 || EXAMINE or DEPOSIT or READ IN
+| 1 || EXAMINE, DEPOSIT, or READ IN (first word)
 |-
-| 2 ||
+| 2 || READ IN (last word)
 |-
-| 3 || EXAMINE NEXT or DEPOSIT NEXT or READ IN
+| 3 || EXAMINE NEXT, DEPOSIT NEXT, or READ IN
 |-
 | 5 || IO RESET
 |-
 | 6 || START
 |}

@@ Line 243: / Line 243: @@
 * 21: MBO +1 PCI CONT CMA/12<br>MBO puts MB into the adder, and +1 increments the address by one.  The sum is put into PC.
 * The read portion of the memory cycle is now ready.  Random logic sets SAO and MBI, which transfers data from the memory SA "sense amplifiers" to MB.
-* 12: IRI ACO ARI CMA/24<br>IRI sets the IR register from SA.  ACO and ARI copies the accumulator contents to the AR register.
+* 12: IRI ACO ARI CMA/24<br>IRI sets the five-bit IR register from SA; four bits are for the opcode and the last bit is for address indirection.  ACO and ARI copies the accumulator contents to the AR register.
 * 24: TI SM CMA/30<br>TI makes a check for indirect addressing.  SM starts a new memory access to retrieve the instruction operand.
 * A new memory cycle starts, reading MB into MA.
 * At this point, CMA 30 may be "boosted" by random logic.  If there's indirect addressing, processing continues at CMA 31.  If the IR holds a CAL, DAC, JMS, or DZM instruction, processing continues at 32.  Otherwise, proceed to the unboosted address 30.
 ** 30: DEI CJIT CMA/60<br>DEI ensures MBI and SAO are set to retrieve the memory operand.  CJIT activates a check for ISZ with operand 0, and increments the PC if so.  The next CMA is "boosted" by putting the instruction opcode in the lower four bits, thus dispatching to CMA 60-77.
-** 31: DEI CMA/24<br>DEI clears the indirect addressing bit.  The memory cycle read phase has put the indirect address in MB.  Processing loops back to CMA 24 to start a new memory cycle using MB as the address.
+** 31: DEI CMA/24<br>DEI clears the indirect addressing bit in IR4.  The memory cycle read phase has put the indirect address in MB.  Processing loops back to CMA 24 to start a new memory cycle using MB as the address.  There can't be any more loop since IR4 was cleared.
 ** 32: ARI PCO CONT CMA/23<br>The PC is saved in the AR register for the benefit of CAL and JMS; later it will be written to memory location MA.<br>23: MBO +1 CJIT CONT CMA/60<br>MBO sends the MB through the adder, and +1 increments it.  CJIT checks for CAL or JMS to set PCI and store the incremented result to the PC.  Dispatch to CMA 60-77.
 * The instruction execute phase dispatches to the CMA region 60-77.  The memory cycle read phase has put the operand in MB, and the write phase is ready to receive the result.  Three instructions, XCT, EAE, and IOT, have a more complicated flow.

@@ Line 1: / Line 1: @@
 Description of the [[PDP-9]] [[Microcode|control memory]] contents.  The control memory is a read-only [[core memory]] which consists of 64 ''process words'' (i.e. microwords) of 36 bits each.
 ===Program listing===
@@ Line 266: / Line 261: @@
 Each process word in the region 60-77 implements the execution phase of one of the 16 PDP-9 instructions.

@@ Line 261: / Line 261: @@
 ** '''IOT''' 76: CMA/20<br>Random logic does all the work for the I/O transfer instructions.<br>20: DONE CONT CMA/10<br>Finish I/O and loop back to CMA 10.
-The control memory region 11-37 is shared with instruction flow, but also implements data break, interrupt, and console panel deposit and examine functions.
+The control memory region 11-37 is shared with instruction flow, but also implements data break, interrupt, and console panel deposit, examine, and read-in functions.
 Region 40-57 is dedicated to the EAE instructions.
 Each process word in the region 60-77 implements the execution phase of one of the 16 PDP-9 instructions.

@@ Line 238: / Line 238: @@
 ===Explanation===
-When the machine is powered on, control memory loops in a "nop" word at CMA 00.  When the START switch is pressed, the CMA is "boosted" to 06 by random logic decoding the state of the switches.
+The control memory region 00-07 is dedicated to implementing actions for the console panel switches.  When the machine is powered on, control memory loops in a "nop" word at CMA 00.  When the START switch is pressed, the CMA is "boosted" to 06 by random logic decoding the state of the switches.
 * 06: ADSO MBI PCI SM CMA/21<br>ADSO gates output from the address switches; MBI and PCI gates input to the MB and PC registers.  SM starts a new memory cycle.  Processing enters the fetch phase at CMA 21.
-The normal start of the instruction flow is at CMA 10.  All instructions end by looping back there.
+The control memory region 10-33 is mostly dedicated to fetch, defer, and execute instruction cycles.  The normal start of the instruction flow is at CMA 10.  All instructions end by looping back there.
 * 10: PCO SM CMA/21<br>PCO gates output from the PC register.  Random logic sets MBI which gates input to the MB register, thus setting it to PC.  SM starts memory access.
@@ Line 260: / Line 260: @@
 ** '''EAE''' 75: EAE ACO ARI LI CONT CMA/43<br>Extended arithmetic is implemented in CMA 40-57 and will eventually reach a process word with DONE CONT CMA/10.
 ** '''IOT''' 76: CMA/20<br>Random logic does all the work for the I/O transfer instructions.<br>20: DONE CONT CMA/10<br>Finish I/O and loop back to CMA 10.