Pipeline - Revision history

Jnc: Now that I think about it, not really a 'basic' concept

2018-12-15T13:49:33Z

Now that I think about it, not really a 'basic' concept

← Older revision		Revision as of 13:49, 15 December 2018
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	{{semi-stub}}		{{semi-stub}}

	[[Category: CPU ~~Basics‎‎~~]]		[[Category: CPU Hardware]]

Jnc: better cat

2018-12-14T21:55:24Z

better cat

← Older revision		Revision as of 21:55, 14 December 2018
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	{{semi-stub}}		{{semi-stub}}

	[[Category: ~~Hardware~~ Basics‎‎]]		[[Category: CPU Basics‎‎]]

Jnc: +cat

2018-12-13T03:09:02Z

+cat

← Older revision		Revision as of 03:09, 13 December 2018
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	A '''pipeline''' is a way of arranging the internal [[logic]] in a [[Central Processing Unit\|CPU]] to increase the processing capacity of that CPU. It organizes the processing of an [[instruction]] into several discrete stages, and then allows each stage to be occupied simultaneously by different instructions.		A '''pipeline''' is a way of arranging the internal [[logic]] in a [[Central Processing Unit\|CPU]] to increase the processing capacity of that CPU. It organizes the processing of an [[instruction]] into several discrete sequential stages, and then allows each stage to be occupied simultaneously by different instructions.

	Thus, while the time to execute a ''particular'' instruction, from beginning to end, is the basic [[clock]] rate times the number of pipeline stages, each clock tick will generally see the completion of the [[execute\|execution]] of ''an'' instruction. (The caveat is because in complex CPUs, execution of an instruction is sometimes 'stalled' for various reasons.)		Thus, while the time to execute a ''particular'' instruction, from beginning to end, is the basic [[clock]] rate times the number of pipeline stages, each clock tick will generally see the completion of the [[execute\|execution]] of ''an'' instruction. (The caveat is because in complex CPUs, execution of an instruction is sometimes 'stalled' for various reasons.)

	{{semi-stub}}		{{semi-stub}}

			[[Category: Hardware Basics‎‎]]

Jnc: Proper cat, +links

2018-10-20T16:19:01Z

Proper cat, +links

← Older revision		Revision as of 16:19, 20 October 2018
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	A '''pipeline''' is a way of arranging the internal ~~circuitry~~ in a [[Central Processing Unit\|CPU]] to increase the processing capacity of that CPU. It organizes the processing of an [[instruction]] into several discrete stages, and then allows each stage to be occupied simultaneously by different instructions.		A '''pipeline''' is a way of arranging the internal [[logic]] in a [[Central Processing Unit\|CPU]] to increase the processing capacity of that CPU. It organizes the processing of an [[instruction]] into several discrete stages, and then allows each stage to be occupied simultaneously by different instructions.

	Thus, while the time to execute a ''particular'' instruction, from beginning to end, is the basic clock rate times the number of pipeline stages, each clock tick will generally see the completion of the execution of ''an'' instruction. (The caveat is because in complex CPUs, execution of an instruction is sometimes 'stalled' for various reasons.)		Thus, while the time to execute a ''particular'' instruction, from beginning to end, is the basic [[clock]] rate times the number of pipeline stages, each clock tick will generally see the completion of the [[execute\|execution]] of ''an'' instruction. (The caveat is because in complex CPUs, execution of an instruction is sometimes 'stalled' for various reasons.)

	{{stub}}		{{semi-stub}}

Jnc: Clearer

2018-04-20T16:21:18Z

Clearer

← Older revision		Revision as of 16:21, 20 April 2018
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	A '''pipeline''' is a way of arranging the internal circuitry in a [[Central Processing Unit\|CPU]] to increase the processing ~~speed~~ of that CPU. It organizes the processing of an [[instruction]] into several discrete stages, and then allows each stage to be occupied simultaneously by different instructions.		A '''pipeline''' is a way of arranging the internal circuitry in a [[Central Processing Unit\|CPU]] to increase the processing capacity of that CPU. It organizes the processing of an [[instruction]] into several discrete stages, and then allows each stage to be occupied simultaneously by different instructions.

	Thus, while the time to execute a ''particular'' instruction, from beginning to end, is the basic clock rate times the number of pipeline stages, each clock tick will generally see the completion of the execution of ''an'' instruction. (The caveat is because in complex CPUs, execution is sometimes 'stalled' for various reasons.)		Thus, while the time to execute a ''particular'' instruction, from beginning to end, is the basic clock rate times the number of pipeline stages, each clock tick will generally see the completion of the execution of ''an'' instruction. (The caveat is because in complex CPUs, execution of an instruction is sometimes 'stalled' for various reasons.)

	{{stub}}		{{stub}}

Jnc: A start

2018-04-20T13:46:31Z

A start

New page

A '''pipeline''' is a way of arranging the internal circuitry in a [[Central Processing Unit|CPU]] to increase the processing speed of that CPU. It organizes the processing of an [[instruction]] into several discrete stages, and then allows each stage to be occupied simultaneously by different instructions.

Thus, while the time to execute a ''particular'' instruction, from beginning to end, is the basic clock rate times the number of pipeline stages, each clock tick will generally see the completion of the execution of ''an'' instruction. (The caveat is because in complex CPUs, execution is sometimes 'stalled' for various reasons.)

{{stub}}