Private Memory Interconnect - Revision history

Jnc: Link new page KDJ11 PMI/UNIBUS backplane

2024-10-08T11:28:14Z

Link new page KDJ11 PMI/UNIBUS backplane

← Older revision		Revision as of 11:28, 8 October 2024
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	The '''Private Memory Interconnect (PMI)''' bus was a high-performance [[bus]], a variant of the [[QBUS]], introduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit\|CPU]] and a [[KTJ11-B UNIBUS adapter\|KTJ11-B]] [[UNIBUS]] adapter to communicate in providing UNIBUS service.		The '''Private Memory Interconnect (PMI)''' bus was a high-performance [[bus]], a variant of the [[QBUS]], introduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit\|CPU]] and a [[KTJ11-B UNIBUS adapter\|KTJ11-B]] [[UNIBUS]] adapter to communicate in providing UNIBUS service.

	For data transfer to [[main memory]], PMI provides two primary modes~~; i)~~ single- and double-word data reads, and single-word and single-byte writes; ~~ii)~~ block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform [[Direct Memory Access\|DMA]] cycles (mapped to the full 22-bit address space via a [[UNIBUS map]]), and to interrupt the CPU.		For data transfer to [[main memory]], PMI provides two primary modes:

			* single- and double-[[word]] data reads, and single-word and single-byte writes;
			* block mode, which can read up to 16 words.

			When operating with a KTJ11-B, it provides means for UNIBUS devices to perform [[Direct Memory Access\|DMA]] cycles (mapped to the full 22-bit [[address space]] via a [[UNIBUS map]]), and to [[interrupt]] the CPU.

	The PMI uses the [[CD interconnect]] specified for some QBUS [[backplane]]s to carry PMI-specific [[signal]]s; PMI also uses other existing QBUS signals (e.g. BDAL00-21), on their standard pins. Note that PMI and QBUS devices and memories can co-exist on the same physical bus; for example, in a [[PDP-11/83]] system, the CPU will use PMI to talk to the main memory, but DMA devices on the QBUS will use normal QBUS [[protocol]]s to talk to that same memory.		The PMI uses the [[CD interconnect]] specified for some QBUS [[backplane]]s to carry PMI-specific [[signal]]s; PMI also uses other existing QBUS signals (e.g. BDAL00-21), on their standard pins. Note that PMI and QBUS devices and memories can co-exist on the same physical bus; for example, in a [[PDP-11/83]] system, the CPU will use PMI to talk to the main memory, but DMA devices on the QBUS will use normal QBUS [[protocol]]s to talk to that same memory.

	Use of the standard CD interconnect means that PMI-based systems (such as the -11/83) can be constructed with a standard [[QBUS#Backplanes\|Q/CD backplane]], a KDJ11-B CPU card, and one or more [[PMI memories]]. The [[PDP-11/84]] ~~has~~ a special backplane with a slightly modified form of CD interconnect for its PMI (below).		Use of the standard CD interconnect means that PMI-based systems (such as the -11/83) can be constructed with a standard [[QBUS#Backplanes\|Q/CD backplane]], a KDJ11-B CPU card, and one or more [[PMI memories]]. The [[PDP-11/84]] and [[PDP-11/94]] have a special backplane with a slightly modified form of CD interconnect for its PMI (below).

	==CD interconnect details==		==CD interconnect details==
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	So, instead, PMI CPU cards emit the PMI bus on their '''''top''''' CD connector pins, and the memory cards take the bus in on their '''''bottom''''' pins, and repeat it through to their '''''top''''' pins. Thus, PMI memory cards must be placed in a Q/CD backplane '''''above''''' the CPU card.		So, instead, PMI CPU cards emit the PMI bus on their '''''top''''' CD connector pins, and the memory cards take the bus in on their '''''bottom''''' pins, and repeat it through to their '''''top''''' pins. Thus, PMI memory cards must be placed in a Q/CD backplane '''''above''''' the CPU card.

	An exception to this rule is the backplane in the ~~[[PDP~~-11/84]], in which the CD connectors of the QBUS section of the backplane are wired to form a true bus; in this machine, the PMI memory cards are placed ''below'' the processor card.		An exception to this rule is the [[KDJ11 PMI/UNIBUS backplane\|special backplane]] in the -11/84 and -11/94, in which the CD connectors of the QBUS section of the backplane are wired to form a true bus; in this machine, the PMI memory cards are placed ''below'' the processor card.

	==Pinout==		==Pinout==
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	PMI pins are identified in the standard [[DEC edge connector contact identification\|DEC manner]]; there are four connectors, A-B; pins on the component side are 1, those on the solder side are 2. Pins are identified by the '[[DEC alphabet]]', A-V, with G, I, O and Q dropped.		PMI pins are identified in the standard [[DEC edge connector contact identification\|DEC manner]]; there are four connectors, A-B; pins on the component side are 1, those on the solder side are 2. Pins are identified by the '[[DEC alphabet]]', A-V, with G, I, O and Q dropped.

	The tables below show the pins used for normal PMI master-slave cycles (as in the PDP-11/83), and those used to communicate with the KTJ11-B UNIBUS adapter (~~PDP~~-11/84 and ~~PDP~~-11/94 only).		The tables below show the pins used for normal PMI master-slave cycles (as in the PDP-11/83), and those used to communicate with the KTJ11-B UNIBUS adapter (-11/84 and -11/94 only).

	===Master-slave signals===		===Master-slave signals===

Jnc: +New category

2024-02-06T15:11:40Z

+New category

← Older revision		Revision as of 15:11, 6 February 2024
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	[[Category: DEC Buses]]		[[Category: DEC Buses]]
			[[Category: Private Memory Interconnect]]

Jnc: rm bloat

2023-07-02T16:10:06Z

rm bloat

← Older revision		Revision as of 16:10, 2 July 2023
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	* [[PMI memories]]		* [[PMI memories]]

	~~{{PDP-11}}~~

	[[Category: DEC Buses]]		[[Category: DEC Buses]]

Jnc: Avoid redirs, +links

2021-02-09T21:38:51Z

Avoid redirs, +links

← Older revision		Revision as of 21:38, 9 February 2021
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	The '''Private Memory Interconnect (PMI)''' bus was a high-performance [[bus]], a variant of the [[QBUS]], introduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit\|CPU]] and a [[KTJ11-B]] [[UNIBUS]] adapter to communicate in providing UNIBUS service.		The '''Private Memory Interconnect (PMI)''' bus was a high-performance [[bus]], a variant of the [[QBUS]], introduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit\|CPU]] and a [[KTJ11-B UNIBUS adapter\|KTJ11-B]] [[UNIBUS]] adapter to communicate in providing UNIBUS service.

	For data transfer to [[main memory]], PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte writes; ii) block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform DMA cycles (mapped to the full 22-bit address space via a UNIBUS map), and to interrupt the CPU.		For data transfer to [[main memory]], PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte writes; ii) block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform [[Direct Memory Access\|DMA]] cycles (mapped to the full 22-bit address space via a [[UNIBUS map]]), and to interrupt the CPU.

	The PMI uses the [[CD interconnect]] specified for some QBUS [[backplane]]s to carry PMI-specific ~~signals~~; PMI also uses other existing QBUS signals (e.g. BDAL00-21), on their standard pins. Note that PMI and QBUS devices and memories can co-exist on the same physical bus; for example, in a [[PDP-11/83]] system, the CPU will use PMI to talk to the main memory, but DMA devices on the QBUS will use normal QBUS [[protocol]]s to talk to that same memory.		The PMI uses the [[CD interconnect]] specified for some QBUS [[backplane]]s to carry PMI-specific [[signal]]s; PMI also uses other existing QBUS signals (e.g. BDAL00-21), on their standard pins. Note that PMI and QBUS devices and memories can co-exist on the same physical bus; for example, in a [[PDP-11/83]] system, the CPU will use PMI to talk to the main memory, but DMA devices on the QBUS will use normal QBUS [[protocol]]s to talk to that same memory.

	Use of the standard CD interconnect means that PMI-based systems (such as the -11/83) can be constructed with a standard [[QBUS#Backplanes\|Q/CD backplane]], a KDJ11-B CPU card, and one or more [[PMI memories]]. The [[PDP-11/84]] has a special backplane with a slightly modified form of CD interconnect for its PMI (below).		Use of the standard CD interconnect means that PMI-based systems (such as the -11/83) can be constructed with a standard [[QBUS#Backplanes\|Q/CD backplane]], a KDJ11-B CPU card, and one or more [[PMI memories]]. The [[PDP-11/84]] has a special backplane with a slightly modified form of CD interconnect for its PMI (below).
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	\| CV1 \|\| PUBTMO \|\| UNIBUS timeout		\| CV1 \|\| PUBTMO \|\| UNIBUS timeout
	\|}		\|}

			Some PMI memory cards read the PUBMEM signal.

	==See also==		==See also==

Jnc: Move CD use details here, from CD interconnect

2021-02-09T21:19:17Z

Move CD use details here, from CD interconnect

← Older revision		Revision as of 21:19, 9 February 2021
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	The '''Private Memory Interconnect (PMI)''' bus was a high-performance ~~memory~~ bus, a variant of the [[QBUS]], introduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit\|CPU]] and a [[KTJ11-B]] [[UNIBUS]] adapter to communicate in providing UNIBUS service.		The '''Private Memory Interconnect (PMI)''' bus was a high-performance [[bus]], a variant of the [[QBUS]], introduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit\|CPU]] and a [[KTJ11-B]] [[UNIBUS]] adapter to communicate in providing UNIBUS service.

	For data transfer, PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte ~~reads~~; ii) block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform DMA cycles (mapped to the full 22-bit address space via a UNIBUS map), and to interrupt the CPU.		For data transfer to [[main memory]], PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte writes; ii) block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform DMA cycles (mapped to the full 22-bit address space via a UNIBUS map), and to interrupt the CPU.

			The PMI uses the [[CD interconnect]] specified for some QBUS [[backplane]]s to carry PMI-specific signals; PMI also uses other existing QBUS signals (e.g. BDAL00-21), on their standard pins. Note that PMI and QBUS devices and memories can co-exist on the same physical bus; for example, in a [[PDP-11/83]] system, the CPU will use PMI to talk to the main memory, but DMA devices on the QBUS will use normal QBUS [[protocol]]s to talk to that same memory.

	~~The~~ PMI ~~uses~~ the [[CD ~~interconnect~~]] ~~specified for some QBUS~~ [[~~backplane~~]]~~s to carry PMI~~-~~specific signals;~~ PMI ~~also uses other existing QBUS signals~~ (~~e.g. BDAL00-21~~)~~, on their standard pins~~.		Use of the standard CD interconnect means that PMI-based systems (such as the -11/83) can be constructed with a standard [[QBUS#Backplanes\|Q/CD backplane]], a KDJ11-B CPU card, and one or more [[PMI memories]]. The [[PDP-11/84]] has a special backplane with a slightly modified form of CD interconnect for its PMI (below).

	~~Use of the standard~~ CD interconnect means that PMI systems (such as a [[PDP-11/83]]) can be constructed with a standard [[QBUS#Backplanes\|Q/CD backplane]], a KDJ11-B CPU card, and one or more [[QBUS memories\|PMI memories]]. The [[PDP-11/84]] has a special backplane with a slightly modified form of CD interconnect for its PMI.		==CD interconnect details==

	~~Note that~~ PMI ~~and QBUS devices and memories can co~~-~~exist on~~ the ~~same physical~~ bus; in an -~~11/83 system~~, the ~~CPU~~ will use PMI to ~~talk~~ to the ~~memory~~, ~~but DMA devices on~~ the QBUS ~~will use normal QBUS methods~~ to ~~talk to that same~~ memory.		The use of the CD interconnect is somewhat idiosyncratic, because it is desirable to be able to plug in a variable number of memory cards - i.e. create a true 'bus', by connecting together more than two slots. The nature of the CD interconnect, which groups slots into pairs, would normally make this difficult.

			If the CPU card sent out the PMI bus on the bottom ([[DEC card form factor#Edge connector contact identification\|2]], or solder-side) pins, then the memory card would have to take the PMI bus in on its top (1, component-side) pins, and repeat the bus through on its bottom pins, for use by a notional 'next memory card'. However, if the next card is ''not'' a PMI memory card, this will result in the PMI bus being sent to a card which does not use it - possibly with harmful effects.

			So, instead, PMI CPU cards emit the PMI bus on their '''''top''''' CD connector pins, and the memory cards take the bus in on their '''''bottom''''' pins, and repeat it through to their '''''top''''' pins. Thus, PMI memory cards must be placed in a Q/CD backplane '''''above''''' the CPU card.

			An exception to this rule is the backplane in the [[PDP-11/84]], in which the CD connectors of the QBUS section of the backplane are wired to form a true bus; in this machine, the PMI memory cards are placed ''below'' the processor card.

	==Pinout==		==Pinout==
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	\| CK1 \|\| PLBPAR \|\| Low byte parity		\| CK1 \|\| PLBPAR \|\| Low byte parity
	\|}		\|}

			In PMI memory cards such as the [[MSV11-R memory module\|MSV11-R]], these signals are all connected to the solder-side (2) pins, as well as the component-side (1) pins.

	===UNIBUS adapter communication signals===		===UNIBUS adapter communication signals===

Jnc: /* See also */ better target

2020-12-13T23:44:28Z

Jnc: + See also

2018-07-22T17:56:58Z

+ See also

← Older revision		Revision as of 17:56, 22 July 2018
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	\| CV1 \|\| PUBTMO \|\| UNIBUS timeout		\| CV1 \|\| PUBTMO \|\| UNIBUS timeout
	\|}		\|}

			==See also==

			* [[MSV11-J QBUS memory]]

	{{PDP-11}}		{{PDP-11}}

	[[Category: DEC Buses]]		[[Category: DEC Buses]]

Jnc: Mention special -11/84 PMI slots

2018-07-02T18:26:39Z

Mention special -11/84 PMI slots

← Older revision		Revision as of 18:26, 2 July 2018
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	For data transfer, PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte reads; ii) block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform DMA cycles (mapped to the full 22-bit address space via a UNIBUS map), and to interrupt the CPU.		For data transfer, PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte reads; ii) block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform DMA cycles (mapped to the full 22-bit address space via a UNIBUS map), and to interrupt the CPU.

	The PMI uses the [[CD interconnect]] specified for QBUS ~~backplanes~~ to carry PMI-specific signals; PMI also uses other existing QBUS signals (e.g. BDAL00-21), on their standard pins. Use of the standard CD interconnect means that PMI systems (such as a [[PDP-11/83]]) can be constructed with a standard [[QBUS#Backplanes\|Q/CD backplane]], a KDJ11-B CPU card, and one or more [[QBUS memories\|PMI memories]].		The PMI uses the [[CD interconnect]] specified for some QBUS [[backplane]]s to carry PMI-specific signals; PMI also uses other existing QBUS signals (e.g. BDAL00-21), on their standard pins.

			Use of the standard CD interconnect means that PMI systems (such as a [[PDP-11/83]]) can be constructed with a standard [[QBUS#Backplanes\|Q/CD backplane]], a KDJ11-B CPU card, and one or more [[QBUS memories\|PMI memories]]. The [[PDP-11/84]] has a special backplane with a slightly modified form of CD interconnect for its PMI.

	Note that PMI and QBUS devices and memories can co-exist on the same physical bus; in an -11/83 system, the CPU will use PMI to talk to the memory, but DMA devices on the QBUS will use normal QBUS methods to talk to that same memory.		Note that PMI and QBUS devices and memories can co-exist on the same physical bus; in an -11/83 system, the CPU will use PMI to talk to the memory, but DMA devices on the QBUS will use normal QBUS methods to talk to that same memory.

Jnc: Avoid redir

2018-05-14T00:35:37Z

Avoid redir

← Older revision		Revision as of 00:35, 14 May 2018
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	\|}		\|}

	{{~~pdp~~-11}}		{{PDP-11}}

	[[Category: DEC Buses]]		[[Category: DEC Buses]]

Jnc: Update cat, add links

2018-02-19T22:10:17Z

Update cat, add links

← Older revision		Revision as of 22:10, 19 February 2018
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	The '''Private Memory Interconnect (PMI)''' bus was a high-performance memory bus, a variant of the [[QBUS]], introduced with the [[KDJ11-B]] ~~[[PDP-11]] CPU~~. It also provides means for the CPU and a [[KTJ11-B]] [[UNIBUS]] adapter to communicate in providing UNIBUS service.		The '''Private Memory Interconnect (PMI)''' bus was a high-performance memory bus, a variant of the [[QBUS]], introduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit\|CPU]] and a [[KTJ11-B]] [[UNIBUS]] adapter to communicate in providing UNIBUS service.

	For data transfer, PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte reads; ii) block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform DMA cycles (mapped to the full 22-bit address space via a UNIBUS map), and to interrupt the CPU.		For data transfer, PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte reads; ii) block mode, which can read up to 16 words. When operating with a KTJ11-B, it provides means for UNIBUS devices to perform DMA cycles (mapped to the full 22-bit address space via a UNIBUS map), and to interrupt the CPU.
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	{{pdp-11}}		{{pdp-11}}

	[[Category: ~~Bus Architectures~~]]		[[Category: DEC Buses]]

← Older revision		Revision as of 23:44, 13 December 2020
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	==See also==		==See also==

	* [[~~MSV11-J QBUS memory~~]]		* [[PMI memories]]

	{{PDP-11}}		{{PDP-11}}

	[[Category: DEC Buses]]		[[Category: DEC Buses]]