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		<title>Programmable Logic Array - Revision history</title>
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		<updated>2026-04-19T15:44:33Z</updated>
		<subtitle>Revision history for this page on the wiki</subtitle>
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	<entry>
		<id>https://gunkies.org/w/index.php?title=Programmable_Logic_Array&amp;diff=30746&amp;oldid=prev</id>
		<title>Jnc: Jnc moved page PLA to Programmable Logic Array: Full name</title>
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				<updated>2023-08-03T17:12:13Z</updated>
		
		<summary type="html">&lt;p&gt;Jnc moved page &lt;a href=&quot;/wiki/PLA&quot; class=&quot;mw-redirect&quot; title=&quot;PLA&quot;&gt;PLA&lt;/a&gt; to &lt;a href=&quot;/wiki/Programmable_Logic_Array&quot; title=&quot;Programmable Logic Array&quot;&gt;Programmable Logic Array&lt;/a&gt;: Full name&lt;/p&gt;
&lt;table class=&quot;diff diff-contentalign-left&quot; data-mw=&quot;interface&quot;&gt;
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				&lt;td colspan=&quot;1&quot; style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;← Older revision&lt;/td&gt;
				&lt;td colspan=&quot;1&quot; style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;Revision as of 17:12, 3 August 2023&lt;/td&gt;
				&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; style=&quot;text-align: center;&quot; lang=&quot;en&quot;&gt;&lt;div class=&quot;mw-diff-empty&quot;&gt;(No difference)&lt;/div&gt;
&lt;/td&gt;&lt;/tr&gt;&lt;/table&gt;</summary>
		<author><name>Jnc</name></author>	</entry>

	<entry>
		<id>https://gunkies.org/w/index.php?title=Programmable_Logic_Array&amp;diff=30745&amp;oldid=prev</id>
		<title>Jnc: Do this one too while I am here</title>
		<link rel="alternate" type="text/html" href="https://gunkies.org/w/index.php?title=Programmable_Logic_Array&amp;diff=30745&amp;oldid=prev"/>
				<updated>2023-08-03T17:10:46Z</updated>
		
		<summary type="html">&lt;p&gt;Do this one too while I am here&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;'''Programmable Logic Array''' (usually referred to by the acronym, '''PLA''') is the name for a [[integrated circuit|chips]] which contain a class of configurable blocks of [[logic]] elements; the programming is done with [[fusible link]]s.&lt;br /&gt;
&lt;br /&gt;
They contain programmable [[array]]s of AND [[gate]]s, whose outputs are led into programmable arrays of OR gates. They were later supplemented by [[Programmable Array Logic]] chips, which were less flexible (only their AND arrays were programmable), but therefore simpler.&lt;br /&gt;
&lt;br /&gt;
&amp;lt;!-- ==Further reading==&lt;br /&gt;
&lt;br /&gt;
* ''PAL Programmable Array Logic Handbook'', Monolithic Memories, Inc., Santa Clara&lt;br /&gt;
--&amp;gt;&lt;br /&gt;
[[Category: Technology]]&lt;br /&gt;
[[Category: Integrated Circuits]]&lt;/div&gt;</summary>
		<author><name>Jnc</name></author>	</entry>

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