QBUS - Revision history

Jnc: Clarify multiplexed lines; Bitsavers has reorganized a bit

2026-10-07T19:43:34Z

Clarify multiplexed lines; Bitsavers has reorganized a bit

Jnc: /* External links */ + Q-bus Expansion Concepts

2025-05-30T11:12:47Z

External links: + Q-bus Expansion Concepts

← Older revision		Revision as of 11:12, 30 May 2025
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	* [http://www.bitsavers.org/pdf/dec/vax/handbook/Supermicrosystems_Handbook_1986.pdf Supermicrosystems Handbook] - the QBUS is documented in the very detailed and comprehensive Appendix A, "Q-bus" (pp. 204-255 of the PDF)		* [http://www.bitsavers.org/pdf/dec/vax/handbook/Supermicrosystems_Handbook_1986.pdf Supermicrosystems Handbook] - the QBUS is documented in the very detailed and comprehensive Appendix A, "Q-bus" (pp. 204-255 of the PDF)
	* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/EB-24944-18_Micro_PDP-11_Handbook_1983-84.pdf MICRO/PDP-ll Handbook] - Appendix E: LSI-11 BUS Technical Specifications (pp. 255-301)		* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/EB-24944-18_Micro_PDP-11_Handbook_1983-84.pdf MICRO/PDP-ll Handbook] - Appendix E: LSI-11 BUS Technical Specifications (pp. 255-301)
			* [http://www.bitsavers.org/pdf/dec/qbus/Digital_Microcomputer_Products_Handbook_1985.pdf Microcomputer Products Handbook] (EB-26078-41) - excellent coverage of both the QBUS itself (Chapter 1), and almost all QBUS boards available as of the date of publication
	* [https://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote2.txt Block Mode DMA] ([[MicroNote]] #002)		* [https://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote2.txt Block Mode DMA] ([[MicroNote]] #002)
	* [~~http~~://www.~~bitsavers~~.org/~~pdf~~/~~dec~~/~~qbus~~/~~Digital_Microcomputer_Products_Handbook_1985~~.~~pdf Microcomputer Products Handbook~~] (~~EB-26078-41) - excellent coverage of both the QBUS itself (Chapter 1~~)~~, and almost all QBUS boards available as of the date of publication~~		* [https://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote29.txt Q-bus Expansion Concepts] ([[MicroNote]] #029)
	* [http://www.vaxarchive.org/hardware/vfg/index.html Visual Field Guide] - mostly QBUS boards		* [http://www.vaxarchive.org/hardware/vfg/index.html Visual Field Guide] - mostly QBUS boards
	** [http://www.vaxarchive.org/hardware/vfg/dquad.html Quad Width Boards]		** [http://www.vaxarchive.org/hardware/vfg/dquad.html Quad Width Boards]

Jnc: /* Further reading */ +22-Bit Addressing for DMA Chipkit Users

2024-07-31T22:53:28Z

Further reading: +22-Bit Addressing for DMA Chipkit Users

← Older revision		Revision as of 22:53, 31 July 2024
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	* ''Block Mode DMA'', MicroNote #113		* ''Block Mode DMA'', MicroNote #113
	** ''18-bit DMA with Chipkits'', MicroNote #069		** ''18-bit DMA with Chipkits'', MicroNote #069
			** ''22-Bit Addressing for DMA Chipkit Users'', MicroNote #107
	* ''The LSI-11/23 and the LSI-11/2 Buses are the Same'', MicroNote #079		* ''The LSI-11/23 and the LSI-11/2 Buses are the Same'', MicroNote #079
	* ''Removing Modules from "Live" Backplanes'', MicroNote #042		* ''Removing Modules from "Live" Backplanes'', MicroNote #042

Jnc: /* Further reading */ +The LSI-11/23 and the LSI-11/2 Buses are the Same

2024-07-29T11:04:37Z

Further reading: +The LSI-11/23 and the LSI-11/2 Buses are the Same

← Older revision		Revision as of 11:04, 29 July 2024
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	* ''Block Mode DMA'', MicroNote #113		* ''Block Mode DMA'', MicroNote #113
	** ''18-bit DMA with Chipkits'', MicroNote #069		** ''18-bit DMA with Chipkits'', MicroNote #069
			* ''The LSI-11/23 and the LSI-11/2 Buses are the Same'', MicroNote #079
	* ''Removing Modules from "Live" Backplanes'', MicroNote #042		* ''Removing Modules from "Live" Backplanes'', MicroNote #042

Jnc: /* Further reading */ +LSI-11 vs. LSI-11/23 Transaction Differences

2024-07-29T01:12:45Z

Further reading: +LSI-11 vs. LSI-11/23 Transaction Differences

← Older revision		Revision as of 01:12, 29 July 2024
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	* ''LSI-11/23 Four-Level Interrupts'', MicroNote #059		* ''LSI-11/23 Four-Level Interrupts'', MicroNote #059
	* ''LSI-11 vs. LSI-l1/23 Bus Timing'',MicroNote #055		* ''LSI-11 vs. LSI-l1/23 Bus Timing'',MicroNote #055
			** ''LSI-11 vs. LSI-11/23 Transaction Differences'', MicroNote #070
	* ''Block Mode DMA'', MicroNote #113		* ''Block Mode DMA'', MicroNote #113
	** ''18-bit DMA with Chipkits'', MicroNote #069		** ''18-bit DMA with Chipkits'', MicroNote #069

Jnc: /* Further reading */ +18-bit DMA with Chipkits

2024-07-29T01:10:56Z

Further reading: +18-bit DMA with Chipkits

← Older revision		Revision as of 01:10, 29 July 2024
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	* ''LSI-11 Bus Theory of Operation'', [[MicroNote]] #012 - good overview		* ''LSI-11 Bus Theory of Operation'', [[MicroNote]] #012 - good overview
	* ''LSI-11/23 Four-Level Interrupts'', MicroNote #59		* ''LSI-11/23 Four-Level Interrupts'', MicroNote #059
	* ''LSI-11 vs. LSI-l1/23 Bus Timing'',MicroNote #55		* ''LSI-11 vs. LSI-l1/23 Bus Timing'',MicroNote #055
	* ''Block Mode DMA'', MicroNote #113		* ''Block Mode DMA'', MicroNote #113
			** ''18-bit DMA with Chipkits'', MicroNote #069
	* ''Removing Modules from "Live" Backplanes'', MicroNote #042		* ''Removing Modules from "Live" Backplanes'', MicroNote #042

Jnc: /* Further reading */ LSI-11 vs. LSI-l1/23 Bus Timing

2024-07-28T18:41:57Z

Further reading: LSI-11 vs. LSI-l1/23 Bus Timing

← Older revision		Revision as of 18:41, 28 July 2024
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	* ''LSI-11 Bus Theory of Operation'', [[MicroNote]] #012 - good overview		* ''LSI-11 Bus Theory of Operation'', [[MicroNote]] #012 - good overview
	* ''LSI-11/23 Four-Level Interrupts'', MicroNote #59		* ''LSI-11/23 Four-Level Interrupts'', MicroNote #59
			* ''LSI-11 vs. LSI-l1/23 Bus Timing'',MicroNote #55
	* ''Block Mode DMA'', MicroNote #113		* ''Block Mode DMA'', MicroNote #113
	* ''Removing Modules from "Live" Backplanes'', MicroNote #042		* ''Removing Modules from "Live" Backplanes'', MicroNote #042

Jnc: /* Further reading */ +Removing Modules from "Live" Backplanes

2024-07-27T17:39:19Z

Further reading: +Removing Modules from "Live" Backplanes

← Older revision		Revision as of 17:39, 27 July 2024
Line 257:		Line 257:
	* ''LSI-11/23 Four-Level Interrupts'', MicroNote #59		* ''LSI-11/23 Four-Level Interrupts'', MicroNote #59
	* ''Block Mode DMA'', MicroNote #113		* ''Block Mode DMA'', MicroNote #113
			* ''Removing Modules from "Live" Backplanes'', MicroNote #042

	==External links==		==External links==

Jnc: /* See also */ +QBUS mounting boxes

2024-07-26T15:36:10Z

Jnc: /* See also */ +Upgrading QBUS backplanes

2024-07-26T14:34:28Z

← Older revision		Revision as of 15:36, 26 July 2024
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	* [[UNIBUS and QBUS termination]]		* [[UNIBUS and QBUS termination]]
	* [[Private Memory Interconnect]]		* [[Private Memory Interconnect]]
			* [[QBUS mounting boxes]]
	* [[QBUS backplanes]]		* [[QBUS backplanes]]
	** [[CD interconnect]]		** [[CD interconnect]]

← Older revision		Revision as of 14:34, 26 July 2024
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	==See also==		==See also==

			* [[Upgrading QBUS backplanes]]
	* [[Bus Arbitration on the Unibus and QBUS]]		* [[Bus Arbitration on the Unibus and QBUS]]
	** [[DMA Request and Grant]]		** [[DMA Request and Grant]]

← Older revision		Revision as of 19:43, 7 October 2026
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	While similar to the UNIBUS, both at a high level, in that it supported both [[main memory]] and [[peripheral controller]]s through read-write cycles, [[Direct Memory Access\|DMA]], and [[interrupt]]s, as well as in much of the low-level detail, such as being entirely [[asynchronous]], and using the same driver [[integrated circuit\|chip]]s for its [[wired-OR]] [[transmission line]]s, it differed in a number of ways.		While similar to the UNIBUS, both at a high level, in that it supported both [[main memory]] and [[peripheral controller]]s through read-write cycles, [[Direct Memory Access\|DMA]], and [[interrupt]]s, as well as in much of the low-level detail, such as being entirely [[asynchronous]], and using the same driver [[integrated circuit\|chip]]s for its [[wired-OR]] [[transmission line]]s, it differed in a number of ways.

	The biggest difference was that it used multiplexed [[address bus\|address]] and [[data bus\|data]] ~~lines~~ (to reduce the pin count), as opposed to the separate address and data lines of the UNIBUS. Another was that although it also supported 4 levels of interrupt priority, that support was optional, and used a more complex signalling mechanism, with only a single shared [[bus grant line]], to do so. Later in its life, the QBUS added support for block transfers, to increase the transfer rate of the bus.		The biggest difference was that it used a single set of lines, multiplexed between holding [[address bus\|address]] and [[data bus\|data]] information (to reduce the pin count), as opposed to the separate address and data lines of the UNIBUS. Another was that although it also supported 4 levels of interrupt priority, that support was optional, and used a more complex signalling mechanism, with only a single shared [[bus grant line]], to do so. Later in its life, the QBUS also added support for block transfers, to increase the transfer rate of the bus.

	==Signalling==		==Signalling==
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	Like the UNIBUS, there are three basic kinds of cycles on the QBUS: data read/write cycles (in which a 'master' reads or writes data to/from a 'slave', which is usually, but not always, memory); DMA cycles (in which a device gains control of the bus so that it can do an identical read/write cycle); and interrupt cycles, in which a device causes the [[Central Processing Unit\|CPU]] to perform an interrupt.		Like the UNIBUS, there are three basic kinds of cycles on the QBUS: data read/write cycles (in which a 'master' reads or writes data to/from a 'slave', which is usually, but not always, memory); DMA cycles (in which a device gains control of the bus so that it can do an identical read/write cycle); and interrupt cycles, in which a device causes the [[Central Processing Unit\|CPU]] to perform an interrupt.

	Also like the UNIBUS, all QBUS transactions are asynchronous, and use interlocked request/response signals for control and timing; also, most QBUS signal lines are electrically bi-directional transmission ~~lines~~ (even though some of these are logically uni-directional); only the grant lines (BDMG and BIAK) are physically uni-directional, and are wired in a daisy-chain fashion.		Also like the UNIBUS, all QBUS transactions are asynchronous, and use interlocked request/response signals for control and timing; also, most QBUS signal lines are electrically bi-directional [[transmission line]]s (even though some of these are logically uni-directional); only the grant lines (BDMG and BIAK) are physically uni-directional, and are wired in a daisy-chain fashion.

	Read/write cycles come in the same basic forms as on the UNIBUS: DATI for word reads, DATO for word writes, DATIO for word read-modify-write cycles, and DATOB and DATIOB for byte write/R-M-W cycles. On the UNIBUS, however, two control lines coded the cycle type; on the QBUS, discrete control lines exist for each type of cycle (BDIN and BDOUT, along with BWTBT).		Read/write cycles come in the same basic forms as on the UNIBUS: DATI for word reads, DATO for word writes, DATIO for word read-modify-write cycles, and DATOB and DATIOB for byte write/R-M-W cycles. On the UNIBUS, however, two control lines coded the cycle type; on the QBUS, discrete control lines exist for each type of cycle (BDIN and BDOUT, along with BWTBT).
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	==External links==		==External links==

	* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/~~PDP11_BusHandbook1979~~.pdf pdp11 bus handbook] (EB-17525-20/79-070-14-55)		* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP-11_Bus_Handbook_1979.pdf pdp11 bus handbook] (EB-17525-20/79-070-14-55)
	* [http://www.bitsavers.org/pdf/dec/handbooks/DIGITAL_Microsystems_Handbook_1985.pdf Microsystems Handbook] - documents block mode in the very detailed and comprehensive Appendix A, "Q-bus" (pp. A-17–A-20; pp. 177-180 of the PDF)		* [https://web.archive.org/web/20250502003121/http://www.bitsavers.org/pdf/dec/handbooks/DIGITAL_Microsystems_Handbook_1985.pdf Microsystems Handbook] - documents block mode in the very detailed and comprehensive Appendix A, "Q-bus" (pp. A-17–A-20; pp. 177-180 of the PDF)
	* [http://www.bitsavers.org/pdf/dec/vax/handbook/Supermicrosystems_Handbook_1986.pdf Supermicrosystems Handbook] - the QBUS is documented in the very detailed and comprehensive Appendix A, "Q-bus" (pp. 204-255 of the PDF)		* [http://www.bitsavers.org/pdf/dec/vax/handbook/Supermicrosystems_Handbook_1986.pdf Supermicrosystems Handbook] - the QBUS is documented in the very detailed and comprehensive Appendix A, "Q-bus" (pp. 204-255 of the PDF)
	* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/EB-24944-18_Micro_PDP-11_Handbook_1983-84.pdf MICRO/PDP-ll Handbook] - Appendix E: LSI-11 BUS Technical Specifications (pp. 255-301)		* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/EB-24944-18_Micro_PDP-11_Handbook_1983-84.pdf MICRO/PDP-ll Handbook] - Appendix E: LSI-11 BUS Technical Specifications (pp. 255-301)
	* [http://www.bitsavers.org/pdf/dec/qbus/~~Digital_Microcomputer_Products_Handbook_1985~~.pdf Microcomputer Products Handbook] (EB-26078-41) - excellent coverage of both the QBUS itself (Chapter 1), and almost all QBUS boards available as of the date of publication		* [http://www.bitsavers.org/pdf/dec/qbus/EB-26078-41_Digital_Microcomputer_Products_Handbook_1985.pdf Microcomputer Products Handbook] (EB-26078-41) - excellent coverage of both the QBUS itself (Chapter 1), and almost all QBUS boards available as of the date of publication
	* [https://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote2.txt Block Mode DMA] ([[MicroNote]] #002)		* [https://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote2.txt Block Mode DMA] ([[MicroNote]] #002)
	* [https://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote29.txt Q-bus Expansion Concepts] ([[MicroNote]] #029)		* [https://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote29.txt Q-bus Expansion Concepts] ([[MicroNote]] #029)