RH11 MASSBUS controller - Revision history

Jnc: /* External links */ +FMPS, mauals

2022-02-25T13:40:58Z

‎External links: +FMPS, mauals

Jnc: /* External links */ useful manual

2021-09-24T16:08:35Z

‎External links: useful manual

Jnc: /* Second UNIBUS */ Add bus hog ref

2019-11-24T15:09:35Z

‎Second UNIBUS: Add bus hog ref

Jnc: Org cleanup; RH11-C details

2019-11-24T15:05:44Z

Org cleanup; RH11-C details

Jnc: /* Second UNIBUS */ B grant lines backplane only

2019-11-23T15:50:57Z

‎Second UNIBUS: B grant lines backplane only

Jnc: add some details

2019-11-23T15:42:53Z

add some details

Jnc: /* Backplane layout */ jumpering UNIBI

2019-11-22T13:50:04Z

‎Backplane layout: jumpering UNIBI

Jnc: /* Hardware */ spc location

2019-11-21T23:23:54Z

‎Hardware: spc location

Jnc: Add 18-bit details

2019-11-21T23:11:17Z

Add 18-bit details

Jnc: Add backplane layout

2019-11-21T14:57:33Z

Add backplane layout

@@ Line 90: / Line 90: @@
 ==External links==
 * [http://www.bitsavers.org/pdf/dec/disc/rjs03_rjs04/DEC-11-HRJSA-B-D_RJS04_RJS03_fixed-head_disk_system_maintenance_manual_Aug1974.pdf RJS04/RJS03 fixed-head disk system maintenance manual] (DEC-11-HRJSA-B-D) - contains detailed RH11 information
 [[Category: MASSBUS Controllers]]
 [[Category: UNIBUS Storage Controllers]]

@@ Line 87: / Line 87: @@
 The order of the UNIBUS 'B' in/out and 'A' out slots is apparently to allow the use of an [[M9200 UNIBUS jumper]] to tie the two UNIBI together. (E.g. in the 'disk' RH11 in the KS10, where the CPU needs access to the device registers, interrupts, etc, which are on UNIBUS 'A', but also has to be connected to UNIBUS 'B', for 18-bit data transfers.)
 [[Category: MASSBUS Controllers]]
 [[Category: UNIBUS Storage Controllers]]

@@ Line 15: / Line 15: @@
 If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] [[bus grant]]s.
-The 'A' UNIBUS has a mode where it can do two DMA cycles per grant. The 'B' UNIBUS can operate in so-called 'Bus Hog' mode (enabled by a [[jumper]]); in this mode, the RH11 can do block transfers without going through any UNIBUS [[arbitration]] cycles. The RH11-C ECO breaks such blocks up into 16-word groups.
+The 'A' UNIBUS has a mode where it can do two DMA cycles per grant. The 'B' UNIBUS can operate in so-called 'Bus Hog' mode (enabled by a [[jumper]]); in this mode, the RH11 can do block transfers without going through any UNIBUS [[arbitration]] cycles. (See Section 4.12.10, "BUS HOG Mode", pg. 4-22
 ===18-bit mode===

@@ Line 1: / Line 1: @@
-The '''RH11 MASSBUS controller''' (generally the '''RH11-AB''' model) allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to systems with a [[UNIBUS]], primarily on [[PDP-11]]'s.
+The '''RH11 MASSBUS controller''' allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to systems with a [[UNIBUS]], primarily on [[PDP-11]]'s.
-There is an '''RH11-B''' model; it uses the M9725-YA card; the difference is not known, but involves the two added one-shots in the lower left corner of drawing BCTB.
+There are three models:
 ===Second UNIBUS===
@@ Line 9: / Line 13: @@
 The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. (The interrupt grant lines on UNIBUS 'B" are only present on the backplane, they are not routed to any of the cards.) The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B').
-If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] [[bus grant]]s. A [[jumper]] allows the RH11 to do block transfers on UNIBUS 'B' without going through an [[arbitration]] cycle; the 'A' UNIBUS has a mode where it can do two DMA cycles per grant.
+If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] [[bus grant]]s.
 ===18-bit mode===
-The RH11 has the capability to operate in [[UNIBUS parity#18-bit width|18-bit mode]]; in this mode, the PA and PB UNIBUS [[parity]] lines are used for data bits 16 and 17. The [[PDP-15]] and [[KS10]] made use of this capability, the latter with the '''RH11-C''' model.
+The RH11 has the capability to operate in [[UNIBUS parity#18-bit width|18-bit mode]]; in this mode, the PA and PB UNIBUS [[parity]] lines are used for data bits 16 and 17. The [[PDP-15]] and [[KS10]] made use of this capability, the latter with the RH11-C model.
 Note that 18-bit mode is only available on the 'B' UNIBUS (which must be selected) if a [[jumper]] is removed; see Section 4.16 "Logic Diagram DBCE", pg. 4-28 (65 of the PDF) in the "RH11-AB Option Description" for details.

@@ Line 7: / Line 7: @@
 The RH11 contains connectors and circuitry for two separate UNIBUSes; the second UNIBUS is primarily used on systems with [[multi-port memory]], such as the [[PDP-11/45]].
-The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B').
+The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. (The interrupt grant lines on UNIBUS 'B" are only present on the backplane, they are not routed to any of the cards.) The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B').
 If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] [[bus grant]]s. A [[jumper]] allows the RH11 to do block transfers on UNIBUS 'B' without going through an [[arbitration]] cycle; the 'A' UNIBUS has a mode where it can do two DMA cycles per grant.

@@ Line 1: / Line 1: @@
 The '''RH11 MASSBUS controller''' (generally the '''RH11-AB''' model) allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to systems with a [[UNIBUS]], primarily on [[PDP-11]]'s.
 ===Second UNIBUS===
@@ Line 13: / Line 15: @@
 The RH11 has the capability to operate in [[UNIBUS parity#18-bit width|18-bit mode]]; in this mode, the PA and PB UNIBUS [[parity]] lines are used for data bits 16 and 17. The [[PDP-15]] and [[KS10]] made use of this capability, the latter with the '''RH11-C''' model.
-(The difference between the -AB and -C is currently unknown; the latter used the M7294-YA instead of the M7294 as in the former. Since that card is the MASSBUS data buffer and control, it's likely related to the MASSBUS.)
+(The difference between the -AB and -C is currently unknown; the latter used the M7294-YA instead of the M7294 as in the former. Since that card is the MASSBUS data buffer and control, it's likely related to the data transfer.)
 Note that 18-bit mode is only available on the 'B' UNIBUS (which must be selected) if a [[jumper]] is removed; see Section 4.16 "Logic Diagram DBCE", pg. 4-28 (65 of the PDF) in the "RH11-AB Option Description" for details.
@@ Line 49: / Line 51: @@
 * M688 - UNIBUS Power Fail Driver
-The RH11 backplane also contained three [[Small Peripheral Controller|SPC]] slots in otherwise-unused slots; they are on UNIBUS 'A'.
+The RH11 backplane also contained three [[Small Peripheral Controller|SPC]] slots in otherwise-unused slots; they are on UNIBUS 'A'. The NPG [[bus grant line]] is routed through those slots, so they are fully capable.
 ===Backplane layout===

@@ Line 1: / Line 1: @@
-The '''RH11 MASSBUS controller''' allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to systems with a [[UNIBUS]], primarily [[PDP-11]]'s.
+The '''RH11 MASSBUS controller''' (technically, the '''RH11-AB''') allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to systems with a [[UNIBUS]], primarily on [[PDP-11]]'s.
-The RH11 has the capability to operate in [[UNIBUS parity#18-bit width|18-bit mode]]; in this mode, the PA and PB UNIBUS lines are used for data bits 16 and 17. The [[KS10]] made use of this capability.
+The RH11 has the capability to operate in [[UNIBUS parity#18-bit width|18-bit mode]]; in this mode, the PA and PB UNIBUS [[parity]] lines are used for data bits 16 and 17. The [[KS10]] made use of this capability.
 ==Second UNIBUS==
@@ Line 9: / Line 9: @@
 The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B').
-If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] grants. A jumper allows the RH11 to do block transfers on UNIBUS 'B' without going through an arbitration cycle; the 'A' UNIBUS has a mode where it does two DMA cycles per grant.
+If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] [[bus grant]]s. A [[jumper]] allows the RH11 to do block transfers on UNIBUS 'B' without going through an [[arbitration]] cycle; the 'A' UNIBUS has a mode where it does two DMA cycles per grant.
 ==Registers==
-The RH11 contains 4 registers, plus a share of a fifth; they are
+The RH11 contains 4 [[register]]s, plus a share of a fifth; they are
 * RHCS1 - Control and Status 1 (shared)
@@ Line 25: / Line 25: @@
 ==Hardware==
-The RH11 consisted of a double [[system unit]] [[backplane]] into which plugged a number of cards:
+The RH11 consisted of a double [[system unit]] [[backplane]] (below) into which plugged a number of cards:
 Two of them [[DEC card form factor|hex]]-sized:
@@ Line 32: / Line 32: @@
 * M7295 - BCT - Bus Control
-Two [[DEC card form factor|dual]]-sized cards containing controller logic:
+Two dual-sized cards containing controller logic:
 * M7296 - CSR - Control and Status
 * M7297 - PAC - Parity Generation and Checking
-Three [[DEC card form factor|dual]]-height M5904 MASSBUS transceiver modules.
+Three dual-height M5904 MASSBUS transceiver modules.
-Optionally one or two (see below) [[DEC card form factor|single]]-height cards:
+Optionally one or two single-height cards:
 * M688 - UNIBUS Power Fail Driver
 The RH11 backplane also contained three [[Small Peripheral Controller|SPC]] slots in otherwise-unused slots.
 [[Category: MASSBUS Controllers]]