RH70 MASSBUS controller - Revision history

Jnc: /* External links */ +RH70 Self-Paced Course

2022-02-25T13:45:12Z

‎External links: +RH70 Self-Paced Course

Jnc: typo

2021-04-29T11:35:30Z

typo

Jnc: /* External links */ +2

2021-04-28T20:03:09Z

‎External links: +2

Jnc: cache controls main mem bus access

2021-04-27T14:14:17Z

cache controls main mem bus access

Jnc: +cat

2018-12-07T17:47:39Z

+cat

Jnc: Reasonably complete

2017-10-28T20:21:45Z

Reasonably complete

New page

The '''RH70 MASSBUS controller''' allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to a [[PDP-11/70]].

One the -11/70 side, it contains connections to both the -11/70's [[main memory]] [[cache]] (for data reads and writes from the device), as well as to the [[UNIBUS]] (for [[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]).

The connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory. A write to a main memory location which is stored in the cache invalidates that cache entry.

==Hardware==

Each RH70 (up to a maximum of 4) consisted of a special pre-wired 4-slot section of the CPU's [[backplane]], into which plugged a number of cards:

One [[DEC card form factor|hex]]-sized:

* M8150 - MDP - Data buffer and parity

Three [[DEC card form factor|quad]]-sized:

* M8151 - CST - Control and Status
* M8152 - AWR - Address and Word Count registers
* M8152 - BCT - bus control

Three [[DEC card form factor|dual]]-height M5904 MASSBUS transceiver modules.

==Registers==

The RH70 contains 6 registers, plus a share of a seventh; they are

* RHCS1 - Control and Status 1 (shared)
* RHWC - Word Count
* RHBA - Bus Address
* RHBAE - Bus Address Extension
* RHCS2 - Control and Status 2
* RHCS3 - Control and Status 3
* RHDB - Data Buffer (for maintenance)

As is standard for the MASSBUS, all the other device registers are in the device.

@@ Line 37: / Line 37: @@
 ==External links==
-* [http://www.bitsavers.org/pdf/dec/unibus/CSS-MO-F-5.2-27_RH70_Option_Description_Feb77.pdf RH70 Option Description]
+* [http://www.bitsavers.org/pdf/dec/unibus/CSS-MO-F-5.2-27_RH70_Option_Description_Feb77.pdf RH70/Special Massbus Controller Option Description] (CSS-MO-F-5.2-27)
 * [http://www.bitsavers.org/pdf/dec/unibus/RH70_Engineering_Drawings_Apr75.pdf RH70 Engineering Drawings]
 [[Category: MASSBUS Controllers]]

@@ Line 19: / Line 19: @@
 * M8152 - BCT - bus control
-Three [[DEC card form factor|dual]]-height M5904 MASSBUS transceiver modules.
+Three dual-height M5904 MASSBUS transceiver modules.
 ==Registers==
@@ Line 35: / Line 35: @@
 As is standard for the MASSBUS, all the other device registers are in the device.
-==External links===
+==External links==
 * [http://www.bitsavers.org/pdf/dec/unibus/CSS-MO-F-5.2-27_RH70_Option_Description_Feb77.pdf RH70 Option Description]

← Older revision		Revision as of 20:03, 28 April 2021
Line 34:		Line 34:

	As is standard for the MASSBUS, all the other device registers are in the device.		As is standard for the MASSBUS, all the other device registers are in the device.
		+
		+	==External links===
		+
		+	* [http://www.bitsavers.org/pdf/dec/unibus/CSS-MO-F-5.2-27_RH70_Option_Description_Feb77.pdf RH70 Option Description]
		+	* [http://www.bitsavers.org/pdf/dec/unibus/RH70_Engineering_Drawings_Apr75.pdf RH70 Engineering Drawings]

	[[Category: MASSBUS Controllers]]		[[Category: MASSBUS Controllers]]

@@ Line 3: / Line 3: @@
 One the -11/70 side, it contains connections to both the -11/70's [[main memory]] and [[cache]] (for data reads and writes from the device), as well as to the [[UNIBUS]] (for [[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]).
-The connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory. A write to a main memory location which is stored in the cache invalidates that cache entry.
+The connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory (although the RH70's access to the main memory bus is controlled by the cache). A write to a main memory location which is stored in the cache invalidates that cache entry.
 ==Hardware==

@@ Line 1: / Line 1: @@
 The '''RH70 MASSBUS controller''' allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to a [[PDP-11/70]].
-One the -11/70 side, it contains connections to both the -11/70's [[main memory]] [[cache]] (for data reads and writes from the device), as well as to the [[UNIBUS]] (for [[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]).
+One the -11/70 side, it contains connections to both the -11/70's [[main memory]] and [[cache]] (for data reads and writes from the device), as well as to the [[UNIBUS]] (for [[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]).
 The connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory. A write to a main memory location which is stored in the cache invalidates that cache entry.
@@ Line 34: / Line 34: @@
 As is standard for the MASSBUS, all the other device registers are in the device.