RL11 disk controller - Revision history

Jnc: /* Further reading */ +RL01 Type-in Bootstrap

2024-07-28T19:17:47Z

‎Further reading: +RL01 Type-in Bootstrap

Jnc: try an rename for Category: QBUS Storage Controllers

2023-02-01T00:13:05Z

try an rename for Category: QBUS Storage Controllers

Jnc: clarify

2022-01-08T23:18:27Z

clarify

Jnc: /* External links */ +FMPS, manuals

2022-01-08T16:48:30Z

‎External links: +FMPS, manuals

Jnc: /* Bootstraps */ Note PIC

2021-05-23T20:16:48Z

‎Bootstraps: Note PIC

Jnc: Add details, bootstrap, RL11 image

2021-05-23T19:21:35Z

Add details, bootstrap, RL11 image

Jnc: Better naming system

2020-10-29T16:12:14Z

Better naming system

Jnc: +links

2020-02-04T15:13:45Z

+links

Jnc: Move pic here

2018-06-10T16:50:48Z

Move pic here

Jnc: Add QBUS versions

2018-06-10T16:46:21Z

Add QBUS versions

← Older revision		Revision as of 19:17, 28 July 2024
Line 187:		Line 187:

	Note that the INIT pulse caused by hitting the [[front panel]]'s 'Start' button will clear the Bus Address register, so that the loaded block will be placed at location 0; and the Disk Address register, so that sector 0 will be read. If the drive's heads are not on cylinder 0, since a seek on an RL01/02 is ''relative'', a 'Read Header' command would have to be done before a seek could be commanded (or the [[device driver]] must remember the current cylinder), and that all would require a fair amount of code. To ensure that the drive is on cylinder 0 for the bootstrap, the drive should be power cycled before starting the bootstrap.		Note that the INIT pulse caused by hitting the [[front panel]]'s 'Start' button will clear the Bus Address register, so that the loaded block will be placed at location 0; and the Disk Address register, so that sector 0 will be read. If the drive's heads are not on cylinder 0, since a seek on an RL01/02 is ''relative'', a 'Read Header' command would have to be done before a seek could be commanded (or the [[device driver]] must remember the current cylinder), and that all would require a fair amount of code. To ensure that the drive is on cylinder 0 for the bootstrap, the drive should be power cycled before starting the bootstrap.
		+
		+	==Further reading==
		+
		+	* ''RL01 Type-in Bootstrap'', [[MicroNote]] #063

	==External links==		==External links==

← Older revision		Revision as of 00:13, 1 February 2023
Line 200:		Line 200:

	[[Category: UNIBUS Storage Controllers]]		[[Category: UNIBUS Storage Controllers]]
−	[[Category: QBUS Storage Controllers]]	+	[[Category: QBUS Storage Controllers\|RLV11]]

@@ Line 5: / Line 5: @@
 The RL11 was a [[DEC card form factor|hex]] board, the M7762. The RLV11 consisted of two quad boards, the M8013 and M8014, which used the [[CD interconnect]] to communicate; it was [[program compatible]] with the RL11. The RLV12 was a single quad board, the M8061; it was mostly program compatible, but added a 'Bus Address Extension' [[register]] for use on [[QBUS#Variable address size|Q22]] systems.
-All have a 40-pin [[Berg connector]] holding a [[flat cable]], which runs to a bulkhead-mounted converter from the flat cable to a special inter-drive cable (round in cross-section, with special locking connectors). (If the flat cable is plugged in the wrong way around, nothing is damaged; the drive merely turns on its 'fault' light.)
+All have a 40-pin [[Berg connector]] header holding a [[flat cable]], which runs to a bulkhead-mounted converter from the flat cable to a special inter-drive cable (round in cross-section, with special locking connectors). (If the flat cable is plugged in the wrong way around, nothing is damaged; the drive merely turns on its 'fault' light.)
 The cable runs from the converter to the first drive; up to 4 drives can be connected to a single controller, using a bus running from one drive to the next, with a [[terminator]] in the last drive of the string.
@@ Line 186: / Line 186: @@
 |}
-Note that the INIT pulse caused by hitting the [[front panel]]'s 'Start' button will clear the Bus Adddress register, so that the loaded block will be placed at location 0; and the Disk Address register, so that sector 0 will be read. If the drive's heads are not on cylinder 0, since a seek on an RL01/02 is ''relative'', a 'Read Header' command would have to be done before a seek could be commanded (or the [[device driver]] must remember the current cylinder), and that all would require a fair amount of code. To ensure that the drive is on cylinder 0 for the bootstrap, the drive should be power cycled before starting the bootstrap.
+Note that the INIT pulse caused by hitting the [[front panel]]'s 'Start' button will clear the Bus Address register, so that the loaded block will be placed at location 0; and the Disk Address register, so that sector 0 will be read. If the drive's heads are not on cylinder 0, since a seek on an RL01/02 is ''relative'', a 'Read Header' command would have to be done before a seek could be commanded (or the [[device driver]] must remember the current cylinder), and that all would require a fair amount of code. To ensure that the drive is on cylinder 0 for the bootstrap, the drive should be power cycled before starting the bootstrap.
 ==External links==

@@ Line 187: / Line 187: @@
 Note that the INIT pulse caused by hitting the [[front panel]]'s 'Start' button will clear the Bus Adddress register, so that the loaded block will be placed at location 0; and the Disk Address register, so that sector 0 will be read. If the drive's heads are not on cylinder 0, since a seek on an RL01/02 is ''relative'', a 'Read Header' command would have to be done before a seek could be commanded (or the [[device driver]] must remember the current cylinder), and that all would require a fair amount of code. To ensure that the drive is on cylinder 0 for the bootstrap, the drive should be power cycled before starting the bootstrap.
 [[Category: UNIBUS Storage Controllers]]
 [[Category: QBUS Storage Controllers]]

@@ Line 160: / Line 160: @@
 ==Bootstraps==
-This [[bootstrap]] will load the block at sector 0 of cylinder 0 of drive 0 into [[main memory]] at [[address]] 0:
+This [[bootstrap]] (which is position-independent [[object code]], so it can be placed anywhere; 04000 is good) will load the block at sector 0 of cylinder 0 of drive 0 into [[main memory]] at [[address]] 0:
 {| border=1
@@ Line 186: / Line 186: @@
 |}
-Note that the INIT pulse caused by hitting the [[front panel]]'s 'Start' button will clear the Bus Adddress register, so that the loaded block will be placed at location 0; and the Disk Address register, so that sector 0 will be read. Since a seek on an RL01/02 is ''relative'', a 'Read Header' command must occur first (or the [[device driver]] must remember the current cylinder), and that all would require a fair amount of code, to ensure that the drive is on cylinder 0 for the bootstrap, the drive should be power cycled before starting the bootstrap.
+Note that the INIT pulse caused by hitting the [[front panel]]'s 'Start' button will clear the Bus Adddress register, so that the loaded block will be placed at location 0; and the Disk Address register, so that sector 0 will be read. If the drive's heads are not on cylinder 0, since a seek on an RL01/02 is ''relative'', a 'Read Header' command would have to be done before a seek could be commanded (or the [[device driver]] must remember the current cylinder), and that all would require a fair amount of code. To ensure that the drive is on cylinder 0 for the bootstrap, the drive should be power cycled before starting the bootstrap.
 [[Category: UNIBUS Storage Controllers]]
 [[Category: QBUS Storage Controllers]]

@@ Line 1: / Line 1: @@
-The '''RL11''' disk controllers (the original RL11 for the [[UNIBUS]], and the '''RLV11''' and '''RLV12''' for the [[QBUS]]) were for the [[RL01/02 disk drive|RL01 and RL02]] [[disk|disk drive]]s.
+[[Image:RL11 M7762.jpg|250px|right|thumb|RL11 M7762 card]]
-[[Image:rlv12.jpg|150px|right|thumb|RLV12]]
+The '''RL11''' disk controllers (the original RL11 for the [[UNIBUS]], and the '''RLV11''' and '''RLV12''' for the [[QBUS]]) were for the [[RL01/02 disk drive|RL01 and RL02]] [[disk|disk drive]]s. (These drives protect the data, and [[sector]] headers, with separate [[cyclic redundancy check|CRCs]].)
 The RL11 was a [[DEC card form factor|hex]] board, the M7762. The RLV11 consisted of two quad boards, the M8013 and M8014, which used the [[CD interconnect]] to communicate; it was [[program compatible]] with the RL11. The RLV12 was a single quad board, the M8061; it was mostly program compatible, but added a 'Bus Address Extension' [[register]] for use on [[QBUS#Variable address size|Q22]] systems.
@@ Line 10: / Line 10: @@
 ==Controller capabilities==
 The controller and drive combination can execute 8 different commands:
@@ Line 22: / Line 24: @@
 * Read Data Without Header Check
-Spiral reads and writes (i.e. multi-block reads which start on one [[track]], and overflow to the next) are not supported; multiple separate read/write commands are needed, with a [[seek]] to the next track between each pair.
+Implied [[seek]]s (i.e. setting the disk address, and then starting a read or write operation, which is intended to happen at that address) are not supported; an explicit seek to the desired [[cylinder]] must be performed before the  read or write. (This is in part because the Disk Address register is shared between the cylinder move number, during a seek operation, and the starting sector number, during a read or write operation.) Spiral reads and writes (i.e. multi-block reads which start on one [[track]], and overflow to the next) are also not supported; multiple separate read/write commands are needed, with a seek to the next track between each pair.
 ==Device registers==
@@ Line 44: / Line 46: @@
 ===774400: Control Status Register (RLCS)===
 {{16bit-header}}
-| CERR || DE || NXM || DLT/HNF || DCRC/ HCRC || OPI || colspan=2 | DRVSEL || CRDY || IE || colspan=2 | ADDR EX || colspan=3 | FUNC || DRDY
+| CERR || DE || NXM || DLT/HNF || DCRC/ HCRC || OPI || colspan=2 | DRVSEL || CRDY || IE || colspan=2 | BUS ADDR EX || colspan=3 | FUNC || DRDY
 {{16bit-bitout}}
 ===774402: Bus Address Register (RLBA)===
@@ Line 80: / Line 108: @@
 ===774406: Multipurpose Register (RLMP)===
 During a 'Get Status' command:
@@ Line 106: / Line 139: @@
 |}
-During a 'Read Header' command, three successive reads to the Multipurpose Register will return, on an RL01:
+During a 'Read Header' command, three successive reads to the Multipurpose Register will return in the first word, on an RL01:
 {{16bit-header}}
 | 0 || colspan=8 | CYL ADDR || HD SEL || colspan=6 | SECTOR
@@ Line 116: / Line 149: @@
 {{16bit-bitout}}
-in the first word, all 0's in the second word, and the header [[CRC]] in the third.
+followed by all 0's in the second word, and the header CRC in the third.
 ===774410: Bus Address Extension Register (RLBAE)===
@@ Line 129: / Line 157: @@
 '''Note:''' This register is present in the RLV12 ''only''.
 [[Category: UNIBUS Storage Controllers]]
 [[Category: QBUS Storage Controllers]]

← Older revision		Revision as of 16:50, 10 June 2018
Line 1:		Line 1:
	The '''RL11''' disk controllers (the original RL11 for the [[UNIBUS]], and the '''RLV11''' and '''RLV12''' for the [[QBUS]]) were for the [[RL01 disk drive\|RL01]] and [[RL02 disk drive\|RL02]] [[disk\|disk drive]]s.		The '''RL11''' disk controllers (the original RL11 for the [[UNIBUS]], and the '''RLV11''' and '''RLV12''' for the [[QBUS]]) were for the [[RL01 disk drive\|RL01]] and [[RL02 disk drive\|RL02]] [[disk\|disk drive]]s.
		+
		+	[[Image:rlv12.jpg\|150px\|right\|thumb\|RLV12]]

	The RL11 was a [[DEC card form factor\|hex]] board, the M7762. The RLV11 consisted of two quad boards, the M8013 and M8014, which used the [[CD interconnect]] to communicate; it was program-compatible with the RL11. The RLV12 was a single quad board, the M8061; it was mostly program-compatible, but added a 'Bus Address Extension' [[register]] for use on [[QBUS#Variable address size\|Q22]] systems.		The RL11 was a [[DEC card form factor\|hex]] board, the M7762. The RLV11 consisted of two quad boards, the M8013 and M8014, which used the [[CD interconnect]] to communicate; it was program-compatible with the RL11. The RLV12 was a single quad board, the M8061; it was mostly program-compatible, but added a 'Bus Address Extension' [[register]] for use on [[QBUS#Variable address size\|Q22]] systems.

@@ Line 1: / Line 1: @@
-The '''RL11''' disk controller for the [[UNIBUS]] was for the [[RL01 disk drive|RL01]] and [[RL02 disk drive|RL02]] [[disk|disk drive]]s.
+The '''RL11''' disk controllers (the original RL11 for the [[UNIBUS]], and the '''RLV11''' and '''RLV12''' for the [[QBUS]]) were for the [[RL01 disk drive|RL01]] and [[RL02 disk drive|RL02]] [[disk|disk drive]]s.
-The RL11 was a [[DEC card form factor|hex]] board. It has a 40-pin [[Berg connector]] holding a [[flat cable]], which runs to a bulkhead-mounted converter from the flat cable to a special inter-drive cable (round in cross-section, with special locking connectors).
+The RL11 was a [[DEC card form factor|hex]] board, the M7762. The RLV11 consisted of two quad boards, the M8013 and M8014, which used the [[CD interconnect]] to communicate; it was program-compatible with the RL11. The RLV12 was a single quad board, the M8061; it was mostly program-compatible, but added a 'Bus Address Extension' [[register]] for use on [[QBUS#Variable address size|Q22]] systems.
-(If the flat cable is plugged in the wrong way around, nothing is damaged; the drive merely turns on its 'fault' light.)
+All have a 40-pin [[Berg connector]] holding a [[flat cable]], which runs to a bulkhead-mounted converter from the flat cable to a special inter-drive cable (round in cross-section, with special locking connectors). (If the flat cable is plugged in the wrong way around, nothing is damaged; the drive merely turns on its 'fault' light.)
 The cable runs from the converter to the first drive; up to 4 drives can be connected to a single controller, using a bus running from one drive to the next, with a terminator in the last drive of the string.
@@ Line 24: / Line 24: @@
 ==Device registers==
-The RL11 controller includes 4 read-write [[register]]s:
+The RL11 controller includes 4 (5 for the RLV12) read-write registers:
 {| border=1
@@ Line 36: / Line 36: @@
 |-
 |Multipurpose Register          || RLMP || 774406
 |}
@@ Line 52: / Line 54: @@
 During a 'Seek' command on an RL01:
 {{16bit-header}}
-| 0 || colspan=8 | CYL ADDR DIFF || colspan=2 | RSVD || HD SEL || 0 || DIR || 0 || 1
+| 0 || colspan=8 | CYL ADDR DIFF || colspan=2 | Reserved || HD SEL || 0 || DIR || 0 || 1
 {{16bit-bitout}}
 During a 'Seek' command on an RL02:
 {{16bit-header}}
-| colspan=9 | CYL ADDR DIFF || colspan=2 | RSVD || HD SEL || 0 || DIR || 0 || 1
+| colspan=9 | CYL ADDR DIFF || colspan=2 | Reserved || HD SEL || 0 || DIR || 0 || 1
 {{16bit-bitout}}
@@ Line 72: / Line 74: @@
 During a 'Get Status' command:
 {{16bit-header}}
-| colspan=8 | NOT USED || colspan=4 | MBZ || RESET || 0 || GT STA || 1
+| colspan=8 | Unused || colspan=4 | MBZ || RESET || 0 || GT STA || 1
 {{16bit-bitout}}
@@ Line 119: / Line 121: @@
 {{16bit-bitout}}
-[[Category:UNIBUS Storage Controllers]]
+===774410: Bus Address Extension Register (RLBAE)===