Jnc: Add bootstrap

2021-05-26T19:30:18Z

Add bootstrap

Jnc: Fairly complete

2021-05-26T19:00:03Z

Fairly complete

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The '''RL8-A disk controller''' for the [[OMNIBUS]] [[PDP-8 family|PDP-8s]] was for the [[RL01/02 disk drive|RL01 and RL02]] [[disk|disk drive]]s. It could be set under program control to either 8-bit or 12-bit mode; in the latter, a [[sector]] contained 170 words, with 8 bits left unused. (These drives protect the data, and [[sector]] headers, with separate [[cyclic redundancy check|CRCs]].)

The RL8-A was a [[DEC card form factor|hex]] board, the M8433. It had a 40-pin [[Berg connector]] which receives a special inter-drive cable (round in cross-section, with special locking connectors). The cable runs to the first drive; up to 4 drives can be connected to a single controller, using a bus running from one drive to the next, with a [[terminator]] in the last drive of the string.

It can be configured as device 60/61 (first controller) or 62/63 (second controller); its normal [[data break]] priority is 0, but it can be [[jumper]]ed to use 1 instead.

==Controller capabilities==

The controller and drive combination can execute 8 different commands:

* Maintenance
* Reset
* Get Status
* Seek
* Read Header
* Write Data
* Read Data
* Read Data Without Header Check


==Device instructions==

The RL8-A is controlled with 14 [[instruction]]s:

{| border=1
! Code !! Mnemonic !! Function
|-
| 6600 || RLDC || Clear controller, all register
|-
| 6601 || RLSD || Skip on function done, clear if set
|-
| 6602 || RLMA || Load memory address register
|-
| 6603 || RLCA || Load command register A
|-
| 6604 || RLCB || Load command register B
|-
| 6605 || RLSA || Load sector address register
|-
| 6607 || RLWC || Load word count register
|-
| 6610 || RRER || Read error register
|-
| 6611 || RRWC || Read word count register
|-
| 6612 || RRCA || Read command register A
|-
| 6613 || RRCB || Read command register B
|-
| 6614 || RRSA || Read sector address register
|-
| 6615 || RRSI || Read silo word
|-
| 6617 || RLSE || Skip on composite error, clear if set
|}

==Device registers==

The RL8-A controller includes 7 internal [[register]]s:

{| border=1
! Register !! Abbreviation
|-
|Command Register A || CA
|-
|Command Register B || CB
|-
|Memory Address Register || MA
|-
|Sector Address Register || SA
|-
|Word Count Register || WC
|-
|Error Register || ER
|-
|Silo Buffer Register || SI
|}

===Command Register A===

During a seek:
{{12bit-header}}
| DIR || HS || Unused || colspan=9 | CYL DIFF
{{12bitoctal-bitout}}
DIR - Direction
HS - Head Select
CYL DIFF - Cylinder Difference (distance to move)

During a data read/write:
{{12bit-header}}
| Unused || HS || Unused || colspan=9 | CYL
{{12bitoctal-bitout}}
HS - Head Select
CYL - Cylinder

===Command Register B===

{{12bit-header}}
| Unused || MAIN || MODE || IE || colspan=2 | DRVSEL || colspan=3 | EMA || colspan=3 | FUNC
{{12bitoctal-bitout}}
MAIN - Maintenance
MODE - 12- OR 8-bit mode
IE - Interrupt Enable
DRVSEL - Drive Select
EMA - Extended Memory Address

{| class="wikitable"
! Function Code !! Function
|-
| 0 || Maintenance
|-
| 1 || Reset
|-
| 2 || Get Status
|-
| 3 || Seek
|-
| 4 || Read Header
|-
| 5 || Write Data
|-
| 6 || Read Data
|-
| 7 || Read Data, No Header Check
|}

===Error Register===

{{12bit-header}}
| DCRC/HCRC || OPI || DLT/HNF || colspan=7 | Unused || DE || DRDY
{{12bitoctal-bitout}}
DCRC/HCRC - Data CRC/Header CRC
OPI - Operation Incomplete
DLT/HNF - Data Late / Header Not Found
DE - Drive Error ('Get Status' will provide details)
DRDY - Drive Ready

===Silo Buffer Register===

During a 'Read Header' command - word 0:
{{12bit-header}}
| colspan=4 | Unused || CA0 || HS || colspan=13 | SECTOR
{{12bitoctal-bitout}}

During a 'Read Header' command - word 1:
{{12bit-header}}
| colspan=4 | Unused || colspan=8 | CYLINDER CA8-CA1
{{12bitoctal-bitout}}

During a 'Get Status' command - word 0:
{{12bit-header}}
| colspan=4 | Unused || DT || HS || CO || HO || BH || colspan=3 | STATE
{{12bitoctal-bitout}}

{| class="wikitable"
! State Code !! State
|-
| 0 || Load Cartridge
|-
| 1 || Spin Up
|-
| 2 || Brush Cycle
|-
| 3 || Load Heads
|-
| 4 || Seek
|-
| 5 || Lock On
|-
| 6 || Unload Heads
|-
| 7 || Spin Down
|}

During a 'Get Status' command - word 1:
{{12bit-header}}
| colspan=4 | Unused || WDE || CHE || WL || STO || SPE || WGE || VC || DSE
{{12bitoctal-bitout}}
WDE - Write Data Error
CHE - Current Head Error
WL - Write Lock
STO - Seek Time Out Error
SPE - Spin Error
WGE - Write Gate Error
VC - Volume Check
DSE - Drive Select Error



[[Category: OMNIBUS Storage Controllers]]

@@ Line 93: / Line 93: @@
   HS - Head Select
   CYL - Cylinder
 ===Command Register B===
@@ Line 135: / Line 134: @@
   DE - Drive Error ('Get Status' will provide details)
   DRDY - Drive  Ready
 ===Silo Buffer Register===
@@ Line 152: / Line 150: @@
 | colspan=4 | Unused || DT || HS || CO || HO || BH || colspan=3 | STATE
 {{12bitoctal-bitout}}
 {| class="wikitable"
@@ Line 186: / Line 189: @@
   DSE - Drive Select Error
-<!-- ==Bootstraps==
+==Bootstraps==
 {| border=1
-! Address !! Data !! Mnemonic !! Description
+! Address !! Data !! Comments
 |- style="background-color: #ccccdd;"
-|1000||012700||MOV #174400,R0           ||Move the address of the Control Status register into R0
+|21||7600|| Clear accumulator
 |- style="background-color: #ccccff;"
-|1002||174400||                         || (constant)
+|22||6600|| Clear controller
 |- style="background-color: #ccccdd;"
-|1004||012760||MOV #177400,6(R0)        ||Move block size (negative) into Multipurpose register
+|23||7332|| Generate constant
 |- style="background-color: #ccccff;"
-|1006||177400||                         || (constant)
+|24||6605|| Load SA with 20
 |- style="background-color: #ccccff;"
-|1010||000006||                         || (constant)
+|26||6607|| Load WC
 |- style="background-color: #ccccdd;"
-|1012||012710||MOV #14,@R0              ||Move 'Read Go' command into CSR
+|27||2327|| Generate constant
 |- style="background-color: #ccccff;"
-|1014||000014||                         || (constant)
+|30||6604|| Load CMD B
 |- style="background-color: #ccccdd;"
-|1016||105710||TSTB (R0)                ||Test for 'Done' bit in CSR
+|31||6601||Skip on done
 |- style="background-color: #ccccff;"
-|1020||100376||BPL 1016                 ||Jump backward if not set
+|32||5031||Jump backward if not
 |}
-Note that the INIT pulse caused by hitting the [[front panel]]'s 'Start' button will clear the Bus Adddress register, so that the loaded block will be placed at location 0; and the Disk Address register, so that sector 0 will be read. If the drive's heads are not on cylinder 0, since a seek on an RL01/02 is ''relative'', a 'Read Header' command would have to be done before a seek could be commanded (or the [[device driver]] must remember the current cylinder), and that all would require a fair amount of code. To ensure that the drive is on cylinder 0 for the bootstrap, the drive should be power cycled before starting the bootstrap. -->
+Start at 21; the loaded [[operating system]] will overlay the bootstrap.
 [[Category: OMNIBUS Storage Controllers]]

RL8-A disk controller - Revision history

Jnc: Add bootstrap

Jnc: Fairly complete