S-1 supercomputer - Revision history

Jnc: /* External links */ +Bitsavers

2024-03-01T18:31:45Z

‎External links: +Bitsavers

Jnc: +New category

2024-01-08T00:55:35Z

+New category

Larsbrinkhoff: 36-bit cat.

2023-07-11T11:36:28Z

36-bit cat.

Jnc: Add some detail

2023-01-29T13:31:22Z

Add some detail

Jnc: caches; +image links

2023-01-29T04:20:37Z

caches; +image links

Jnc: /* External links */ +1979 Annual Report: Volume II - Hardware

2023-01-29T03:56:49Z

‎External links: +1979 Annual Report: Volume II - Hardware

Jnc: general description; more links

2023-01-28T19:35:22Z

general description; more links

Jnc: /* External links */ +several, including The Lawrence Livermore Laboratory S-1 project and Stanford University

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‎External links: +several, including The Lawrence Livermore Laboratory S-1 project and Stanford University

Jnc: +cat

2019-08-10T21:26:10Z

+cat

Jnc: Jnc moved page S-1 to S-1 supercomputer

2019-06-24T14:53:51Z

Jnc moved page S-1 to S-1 supercomputer

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 ==External links==
 * [http://www.bitsavers.org/pdf/stanford/cs_techReports/STAN-CS-79-715_S-1_Arch_Man.pdf S-1 Architecture Manual] (STAN-CS-79-715)
 * [https://www.osti.gov/servlets/purl/5991007 The S-1 Project - 1979 Annual Report: Volume I - Architecture]

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-The '''S-1''' was a [[supercomputer]] architecture jointly developed by [[Stanford University]] and [[Lawrence Livermore National Laboratory]]. It was [[MIMD]] [[multi-processor]] using [[shared memory]], all connected through a [[crossbar]] switch.
+The '''S-1''' was a [[supercomputer]] architecture jointly developed by [[Stanford University]] and [[Lawrence Livermore National Laboratory]]. It was [[MIMD]] [[multi-processor]] using [[shared memory]], all units connected through a [[crossbar]] switch, similar to [[C.mmp]].
-Each [[CPU|processor]] had a [[cache]], but coherence between caches was partially in software - one processor could be notified by hardware, on attempting to utilize a given location, that another processor was currently authoritative for that location, and would have to request that the other processor flush its cache of that location.
+Five generations was planned; the uni-processor first generation was intended to have about the processing power of a [[CDC 7600]], but in actuality fell short of that. It was intended that each [[Central Processing Unit|processor]] in a full 16-processor system in the second-generation design would have about the processing power of a [[Cray 1]].
-Five generations was planned, but only two were built the Mark I, and the Mark IIA. Both were [[wire-wrap]]ped; the Mark IIA was implemented in [[emitter-coupled logic|ECL]].
+Each processor had a [[cache]], but coherence between caches was partially in software - one processor could be notified by hardware, on attempting to utilize a given location, that another processor was currently authoritative for that location, and it would have to request that the other processor flush its cache of that location. That communication was to be via what was effectively a [[local area network|LAN]] which ran to all the processors. That LAN was to be a [[bus]] (similar to an [[Ethernet]]) in the initial implementation; it was planned to use a [[slotted ring]] in the later generations.
-The architecture was inspired by the [[PDP-10]]; among other things the [[word]] size was 36 bits. [[Common Lisp]] got many number crunching features from S-1 Lisp.
+Single instances of only the first two generations, the Mark I, and the Mark IIA, were built. Both were [[wire-wrap]]ped, and implemented in [[emitter-coupled logic|ECL]]. The Mark IIA was actually implemented with the help of design tools, including an advanced [[circuit]] [[simulator]], which ran on the Mark I.
-{{stub}}
+The architecture was inspired by the [[PDP-10]], but added support for [[segment]]ation; among other things, the [[word]] size was 36 bits. The [[operating system]] planned for the machine, [[Amber]], was heavily based on [[Multics]]. [[Common Lisp]] got many number crunching features from S-1 [[LISP]].
 ==External links==
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 * [https://people.computing.clemson.edu/~mark/s1.html S-1 Supercomputer (1975-1988)]
-[[Category: Mainframes]]
+[[Category: Supercomputers]]

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-The '''S-1''' was a [[supercomputer]] architecture jointly developed by [[Stanford University]] and [[Lawrence Livermore National Laboratory]]. It was [[MIMD]] [[multi-processor]] using [[shared memory]], all connected through a [[crossbar]] switch The architecture was inspired by the [[PDP-10]]; among other things the [[word]] size was 36 bits.
+The '''S-1''' was a [[supercomputer]] architecture jointly developed by [[Stanford University]] and [[Lawrence Livermore National Laboratory]]. It was [[MIMD]] [[multi-processor]] using [[shared memory]], all connected through a [[crossbar]] switch.
 Five generations was planned, but only two were built the Mark I, and the Mark IIA. Both were [[wire-wrap]]ped; the Mark IIA was implemented in [[emitter-coupled logic|ECL]].
-[[Common Lisp]] got many number crunching features from S-1 Lisp.
+The architecture was inspired by the [[PDP-10]]; among other things the [[word]] size was 36 bits. [[Common Lisp]] got many number crunching features from S-1 Lisp.
 {{stub}}
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 * [http://www-forum.stanford.edu/wiki/index.php/S-1_project S-1 project]
 * [http://infolab.stanford.edu/pub/voy/museum/pictures/S-1.html The Lawrence Livermore Laboratory S-1 project and Stanford University]
 * [https://people.computing.clemson.edu/~mark/s1.html S-1 Supercomputer (1975-1988)]
 [[Category: Mainframes]]

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