Scheme Chip - Revision history

Larsbrinkhoff: /* External links */ Scheme chip wiki and SCHEME-79 simulator.

2026-09-02T06:24:30Z

External links: Scheme chip wiki and SCHEME-79 simulator.

← Older revision		Revision as of 06:24, 2 September 2026
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	* [https://dl.acm.org/doi/pdf/10.1145/62678.62690 Scheme86 - A System for Interpreting Scheme]		* [https://dl.acm.org/doi/pdf/10.1145/62678.62690 Scheme86 - A System for Interpreting Scheme]
	* [https://github.com/larsbrinkhoff/scheme-chip-files Scheme chip files from MIT PDP-10 computers]		* [https://github.com/larsbrinkhoff/scheme-chip-files Scheme chip files from MIT PDP-10 computers]
			* [http://scheme-chip.net/ Wiki about Scheme chips and Lisp machines]
			* [https://github.com/Bradford-Miller/s79-simulator SCHEME-79 simulator]

	[[Category: Microprocessors]]		[[Category: Microprocessors]]

Larsbrinkhoff: Four generations. Link to repository with original files.

2026-09-02T06:08:49Z

Four generations. Link to repository with original files.

← Older revision		Revision as of 06:08, 2 September 2026
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	The '''Scheme Chip'''s were a series of VLSI [[LISP machine]] [[microprocessor]]s intended to run [[Scheme]].		The '''Scheme Chip'''s were a series of VLSI [[LISP machine]] [[microprocessor]]s intended to run [[Scheme]]. There were four generations: SCHEME-78, SCHEME-79, SCHEME-81, and Scheme86.

	{{stub}}		{{stub}}
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	* [https://dspace.mit.edu/bitstream/handle/1721.1/41168/AI_WP_225.pdf The Assq Chip and Its Progeny]		* [https://dspace.mit.edu/bitstream/handle/1721.1/41168/AI_WP_225.pdf The Assq Chip and Its Progeny]
	* [https://dl.acm.org/doi/pdf/10.1145/62678.62690 Scheme86 - A System for Interpreting Scheme]		* [https://dl.acm.org/doi/pdf/10.1145/62678.62690 Scheme86 - A System for Interpreting Scheme]
			* [https://github.com/larsbrinkhoff/scheme-chip-files Scheme chip files from MIT PDP-10 computers]

	[[Category: Microprocessors]]		[[Category: Microprocessors]]

Jnc: +Cat

2023-06-19T18:26:25Z

+Cat

← Older revision		Revision as of 18:26, 19 June 2023
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	The ''Scheme Chip''s were a series of VLSI [[LISP machine]]s intended to run [[Scheme]].		The '''Scheme Chip'''s were a series of VLSI [[LISP machine]] [[microprocessor]]s intended to run [[Scheme]].

	{{stub}}		{{stub}}
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	* [https://dspace.mit.edu/bitstream/handle/1721.1/41168/AI_WP_225.pdf The Assq Chip and Its Progeny]		* [https://dspace.mit.edu/bitstream/handle/1721.1/41168/AI_WP_225.pdf The Assq Chip and Its Progeny]
	* [https://dl.acm.org/doi/pdf/10.1145/62678.62690 Scheme86 - A System for Interpreting Scheme]		* [https://dl.acm.org/doi/pdf/10.1145/62678.62690 Scheme86 - A System for Interpreting Scheme]

			[[Category: Microprocessors]]

Larsbrinkhoff: Stub.

2023-06-16T19:38:28Z

Stub.

New page

The ''Scheme Chip''s were a series of VLSI [[LISP machine]]s intended to run [[Scheme]].

{{stub}}

==External links==

* [https://dspace.mit.edu/bitstream/handle/1721.1/5731/AIM-514.pdf AI memo 514: "Design of LISP-based Processors, or SCHEME: A Dielectric LISP, or Finite Memories Considered Harmful, or LAMBDA: The Ultimate Opcode"]
* [https://dspace.mit.edu/bitstream/handle/1721.1/6334/AIM-559.pdf AI memo 559: "The SCHEME-79 Chip"]
* [https://dspace.mit.edu/bitstream/handle/1721.1/41168/AI_WP_225.pdf The Assq Chip and Its Progeny]
* [https://dl.acm.org/doi/pdf/10.1145/62678.62690 Scheme86 - A System for Interpreting Scheme]