Series 16 instructions - Revision history

Jnc: /* Input-output instructions */ Describe I/O opcodes

2025-08-05T13:26:54Z

Input-output instructions: Describe I/O opcodes

← Older revision		Revision as of 13:26, 5 August 2025
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	! Opcode !! II/FT !! Mnemonic !! Action		! Opcode !! II/FT !! Mnemonic !! Action
	\|-		\|-
	\| ~~140~~ \|\| 00 \|\| OCP \|\| Output control pulse		\| 030 \|\| 00 \|\| OCP \|\| Output control pulse
	\|-		\|-
	\| ~~340~~ \|\| 01 \|\| SKS \|\| Skip if ready set		\| 070 \|\| 01 \|\| SKS \|\| Skip if ready set
	\|-		\|-
	\| ~~540~~ \|\| 10 \|\| INA \|\| Input to A		\| 130 \|\| 10 \|\| INA \|\| Input to A
	\|-		\|-
	\| ~~740~~ \|\| 11 \|\| OTA \|\| Output from A		\| 170 \|\| 11 \|\| OTA \|\| Output from A
	\|}		\|}

			The 'basic' I/O opcode is #14 (030000 in an instruction word); the Indirect/Index bits select one of the 4 classes (above). Function codes are defined per device type.

	{{semi-stub}}		{{semi-stub}}

Jnc: /* Memory reference instructions */ Old, alternate meaning. of 'microcoding'

2025-08-05T09:03:51Z

Memory reference instructions: Old, alternate meaning. of 'microcoding'

← Older revision		Revision as of 09:03, 5 August 2025
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	\|}		\|}

	'Generic A' and skip instructions use [[microcode#Another meaning\|~~'microcoding'~~]] (see below).		'Generic A' and skip instructions use 'microcoding' (in the old, [[microcode#Another meaning\|alternate meaning]], of that term) (see below).

	==Generic instructions==		==Generic instructions==

Jnc: Correct bit names

2025-08-04T23:01:37Z

Correct bit names

← Older revision		Revision as of 23:01, 4 August 2025
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	\|}		\|}

	For opcode '0', the Indirect/~~Flag~~ bits determine the type of the instruction:		For opcode '0', the Indirect/Index bits determine the type of the instruction:

	{\| class="wikitable" style="text-align: center;"		{\| class="wikitable" style="text-align: center;"
	! IF/FT !! Action		! II/FT !! Action
	\|-		\|-
	\| 0 \|\| Type B Generic instructions		\| 0 \|\| Type B Generic instructions
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	{\| class="wikitable" style="text-align: center;"		{\| class="wikitable" style="text-align: center;"
	! Opcode !! IF/FT !! Mnemonic !! Action		! Opcode !! II/FT !! Mnemonic !! Action
	\|-		\|-
	\| 140 \|\| 00 \|\| OCP \|\| Output control pulse		\| 140 \|\| 00 \|\| OCP \|\| Output control pulse

Jnc: Details on 'skip' instructions

2025-08-04T21:54:58Z

Details on 'skip' instructions

← Older revision		Revision as of 21:54, 4 August 2025
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	\| 013 \|\| IMA \|\| Interchange memory and A		\| 013 \|\| IMA \|\| Interchange memory and A
	\|-		\|-
	\| 014 \|\| colspan=2 \| ''Input-output ~~(below)~~''		\| 014 \|\| colspan=2 \| ''[[#Input-output instructions\|Input-output]]''
	\|-		\|-
	\| 015 \|\| LDX/STX \|\| Load X/Store X		\| 015 \|\| LDX/STX \|\| Load X/Store X
Line 47:		Line 47:
	\| 017 \|\| DIV \|\| Divide		\| 017 \|\| DIV \|\| Divide
	\|}		\|}

			For opcode '0', the Indirect/Flag bits determine the type of the instruction:

			{\| class="wikitable" style="text-align: center;"
			! IF/FT !! Action
			\|-
			\| 0 \|\| Type B Generic instructions
			\|-
			\| 1 \|\| [[#Shift instructions\|Shift instructions]]
			\|-
			\| 2 \|\| [[#Skip instructions\|Skip instructions]]
			\|-
			\| 3 \|\| Type A Generic instructions
			\|}

			'Generic A' and skip instructions use [[microcode#Another meaning\|'microcoding']] (see below).

	==Generic instructions==		==Generic instructions==
	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| Opcode		\| colspan=16 \| Opcode
	{{~~16bit~~-bitout}}		{{16bitoctal-bitout}}

			'Generic B' instructions seem to be a fairly mixed bag; some are:

	{\| class="wikitable" style="text-align: center;"		{\| class="wikitable" style="text-align: center;"
Line 65:		Line 83:
	\|-		\|-
	\| 001001 \|\| INH \|\| Inhibit program interrupt		\| 001001 \|\| INH \|\| Inhibit program interrupt
			\|}

			'Generic A' instructions are for manipulating the [[accumulator]] and 'carry' flag; some are:

			{\| class="wikitable" style="text-align: center;"
			! Opcode !! Mnemonic !! Action
	\|-		\|-
	\| 140040 \|\| CRA \|\| Clear A		\| 140040 \|\| CRA \|\| Clear A
Line 93:		Line 117:
	==Skip instructions==		==Skip instructions==
	{{16bit-header}}		{{16bit-header}}
	\| colspan=16 \| ~~Opcode~~		\| colspan=6 \| 100 \|\| R \|\| P \|\| M \|\| E \|\| Z \|\| colspan=4 \| Sense switches \|\| C
	{{~~16bit~~-bitout}}		{{16bitoctal-bitout}}

			{\| class="wikitable" style="text-align: center;"
			! Bit !! Meaning
			\|-
			\| R \|\| '''R'''everse the skip decision
			\|-
			\| P \|\| Accumulator '''P'''ositive
			\|-
			\| M \|\| '''M'''emory Parity Error
			\|-
			\| E \|\| Accumulator '''E'''ven
			\|-
			\| Z \|\| Accumulator '''Z'''ero
			\|-
			\| C \|\| '''C'''-bit Zero
			\|}

			These bits can be 'microcoded' together; some useful combinations (with assigned mnemonics) were:

	{\| class="wikitable" style="text-align: center;"		{\| class="wikitable" style="text-align: center;"
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	{{16bit-header}}		{{16bit-header}}
	\| colspan=10 \| Opcode \|\| colspan=6 \| Count		\| colspan=10 \| Opcode \|\| colspan=6 \| Count
	{{~~16bit~~-bitout}}		{{16bitoctal-bitout}}

	{\| class="wikitable" style="text-align: center;"		{\| class="wikitable" style="text-align: center;"
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	{{16bit-header}}		{{16bit-header}}
	\| colspan=6 \| Opcode \|\| colspan=4 \| Function \|\| colspan=6 \| Device		\| colspan=6 \| Opcode \|\| colspan=4 \| Function \|\| colspan=6 \| Device
	{{~~16bit~~-bitout}}		{{16bitoctal-bitout}}

	{\| class="wikitable" style="text-align: center;"		{\| class="wikitable" style="text-align: center;"
	! FT !! Mnemonic !! Action		! Opcode !! IF/FT !! Mnemonic !! Action
	\|-		\|-
	\| 00 \|\| OCP \|\| Output control pulse		\| 140 \|\| 00 \|\| OCP \|\| Output control pulse
	\|-		\|-
	\| 01 \|\| SKS \|\| Skip if ready set		\| 340 \|\| 01 \|\| SKS \|\| Skip if ready set
	\|-		\|-
	\| 10 \|\| INA \|\| Input to A		\| 540 \|\| 10 \|\| INA \|\| Input to A
	\|-		\|-
	\| 11 \|\| OTA \|\| Output from A		\| 740 \|\| 11 \|\| OTA \|\| Output from A
	\|}		\|}

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	* [http://www.bitsavers.org/pdf/computerControlCompany/ ComputerControlCompany] - documentation at [[Bitsavers]] (extensive)		* [http://www.bitsavers.org/pdf/computerControlCompany/ ComputerControlCompany] - documentation at [[Bitsavers]] (extensive)
	* [http://www.bitsavers.org/pdf/computerControlCompany/ddp-116/ ddp-116]		* [http://www.bitsavers.org/pdf/computerControlCompany/ddp-116/ ddp-116]
			* [http://www.series16.adrianwise.co.uk/ Honeywell Series 16]
			** [http://www.series16.adrianwise.co.uk/programming/microcode.html Micro-coding the DDP-516 Computer]
	* [https://simh.trailing-edge.com/docs/decodingh316.pdf Decoding The H316/H516 “Generic A” Instructions]		* [https://simh.trailing-edge.com/docs/decodingh316.pdf Decoding The H316/H516 “Generic A” Instructions]

	[[Category: Minicomputers]]		[[Category: Minicomputers]]
	[[Category: 16-bit Computers]]		[[Category: 16-bit Computers]]

Jnc: Fairly complete

2025-07-20T21:28:02Z

Fairly complete

New page

'''Series 16 instructions''' are basically the same across all models of the [[Series 16]] line (although some are missing on some models).

Most of the [[instruction]]s are fitted into a basic layout used for the memory reference instructions; specifically, the basic [[opcode]] field is in the same place in all of them (although some instructions 'borrow' bits from other fields).

==Memory reference instructions==
{{16bit-header}}
| Indirect || Index || colspan=4 | Opcode || Sector || colspan=9 | Address
{{16bit-bitout}}

Memory reference instructions can reference i) words in the 'base' sector (normally sector 0), or ii) words in the same sector as that containing the instruction - the choice being controlled by the 'Sector' bit. (An option, "Memory Lockout", is available, which allows the base sector to be relocated; this is utilized in [[time-sharing]] operation.)

The 'Indirect' bit is also called the 'Flag' bit; the 'Index' bit is also called the 'Tag' bit; these become part of the opcode in non-memory-reference instructions. If both are set in an ordinary instruction, indexing takes place before indirection. The indirect address, if used, allows addressing of all locations in memory. The indirect address word also has Flag and Tag bits; normally, there is generally no limit to the number of levels of indirection that can be invoked.

{| class="wikitable" style="text-align: center;"
! Opcode !! Mnemonic !! Action
|-
| 0 || colspan=2 | ''Generic and skip/shift (below)''
|-
| 1 || JMP || Jump
|-
| 2 || LDA || Load A
|-
| 3 || ANA || AND to A
|-
| 4 || STA || Store A
|-
| 5 || ERA || XOR to A
|-
| 6 || ADD || Add
|-
| 7 || SUB || Subtract
|-
| 010 || JST || Jump and Store
|-
| 011 || CAS || Compare
|-
| 012 || IRS || Increment, replace and skip
|-
| 013 || IMA || Interchange memory and A
|-
| 014 || colspan=2 | ''Input-output (below)''
|-
| 015 || LDX/STX || Load X/Store X
|-
| 016 || MPY || Multiply
|-
| 017 || DIV || Divide
|}

==Generic instructions==
{{16bit-header}}
| colspan=16 | Opcode
{{16bit-bitout}}

{| class="wikitable" style="text-align: center;"
! Opcode !! Mnemonic !! Action
|-
| 000000 || HALT || Halt
|-
| 000043 || INK || Input keys
|-
| 000201 || IAB || Interchange A and B
|-
| 000401 || ENB || Enable program interrupt
|-
| 001001 || INH || Inhibit program interrupt
|-
| 140040 || CRA || Clear A
|-
| 140100 || SSP || Set A sign plus
|-
| 140200 || RCB || Reset C bit
|-
| 140401 || CMA || Complement A
|-
| 140500 || SSM || Set A sign minus
|-
| 140600 || SCB || Set C bit
|-
| 141044 || CAR || Clear A, right half
|-
| 141050 || CAL || Clear A, left half
|-
| 141206 || AOA || Add one to A
|-
| 141216 || ACA || Add C to A
|-
| 141340 || ICA || Interchange characters in A
|}

''Not all instructions are listed''

==Skip instructions==
{{16bit-header}}
| colspan=16 | Opcode
{{16bit-bitout}}

{| class="wikitable" style="text-align: center;"
! Opcode !! Mnemonic !! Action
|-
| 100000 || SKP || Unconditional skip
|-
| 100001 || SRC || Skip if C reset
|-
| 100040 || SZE || Skip if A zero
|-
| 100400 || SPL || Skip if A sign plus
|-
| 101000 || NOP || No operation
|-
| 101001 || SSC || Skip if C bit set
|-
| 101040 || SNZ || Skip if A non-zero
|-
| 101400 || SPL || Skip if A sign minus
|}

''Not all instructions are listed''

==Shift instructions==
{{16bit-header}}
| colspan=10 | Opcode || colspan=6 | Count
{{16bit-bitout}}

{| class="wikitable" style="text-align: center;"
! Opcode !! Mnemonic !! Action
|-
| 0400 || LRL || Long right logical
|-
| 0401 || LRS || Long arithmetic right
|-
| 0402 || LRR || Long right rotate
|-
| 0404 || LGR || Logical right
|-
| 0405 || ARS || Arithmetic right
|-
| 0406 || ARR || Logical right rotate
|-
| 0410 || LLL || Long left logical
|-
| 0411 || LLS || Long arithmetic left
|-
| 0412 || LLR || Long left rotate
|-
| 0414 || LGL || Logical left
|-
| 0415 || ALS || Arithmetic left
|-
| 0416 || ALR || Logical left rotate
|}

The shift count is given in [[two's complement]] form.

==Input-output instructions==
{{16bit-header}}
| colspan=6 | Opcode || colspan=4 | Function || colspan=6 | Device
{{16bit-bitout}}

{| class="wikitable" style="text-align: center;"
! FT !! Mnemonic !! Action
|-
| 00 || OCP || Output control pulse
|-
| 01 || SKS || Skip if ready set
|-
| 10 || INA || Input to A
|-
| 11 || OTA || Output from A
|}

{{semi-stub}}

==External links==

* [http://www.bitsavers.org/pdf/computerControlCompany/ ComputerControlCompany] - documentation at [[Bitsavers]] (extensive)
* [http://www.bitsavers.org/pdf/computerControlCompany/ddp-116/ ddp-116]
* [https://simh.trailing-edge.com/docs/decodingh316.pdf Decoding The H316/H516 “Generic A” Instructions]

[[Category: Minicomputers]]
[[Category: 16-bit Computers]]