Small Peripheral Controller - Revision history

Jnc: /* Grants */ link UNIBUS priority plug

2025-07-27T18:01:10Z

‎Grants: link UNIBUS priority plug

Jnc: /* Pinout */ move table here

2022-04-09T21:38:25Z

‎Pinout: move table here

Jnc: clarify grant jumpers

2021-11-17T16:18:44Z

clarify grant jumpers

Jnc: Also CR11

2021-01-29T12:12:39Z

Also CR11

Jnc: /* SPC Extensions */ typo

2019-09-26T13:12:56Z

‎SPC Extensions: typo

Jnc: /* SPC Extensions */ add link

2019-09-26T13:12:25Z

‎SPC Extensions: add link

Jnc: List multi-card controllers

2018-12-08T16:12:20Z

List multi-card controllers

Jnc: New cat

2018-11-17T20:58:54Z

New cat

Jnc: +cat, links

2018-10-17T20:38:35Z

+cat, links

Jnc: Simpler

2018-01-06T01:01:38Z

Simpler

@@ Line 11: / Line 11: @@
 SPC slots were wired to bring all 5 UNIBUS [[bus grant line|grant lines]] through the device; this was performed in rows C (for [[Non-Processor Request and Grant|NPG]]) and D (for BGx).
-The device board generally had a header which routed the grant (and matching request) line for the desired priority level to the [[interrupt]] [[circuit]]ry, and passed the other grant lines through. Un-occupied slots needed to have a [[G727 grant continuity card|G727]] installed.
+The device board generally had a [[UNIBUS priority plug]] header which routed the grant (and matching request) line for the desired priority level to the [[interrupt]] [[circuit]]ry, and passed the other grant lines through. Un-occupied slots needed to have a [[G727 grant continuity card|G727]] installed.
 The NPG grant line generally had a [[jumper]] on the backplane at each slot (between pins CA1 and CB1), which had to be removed if a [[DMA]] device was plugged into that slot, or installed if one was removed; alternatively, a [[G7273 grant continuity card]] could be installed.

@@ Line 21: / Line 21: @@
 In the [[PDP-11/04]] and [[PDP-11/34]], on the [[DD11-P backplane]] which holds the [[Central Processing Unit|CPU]] card(s), along with the [[KY11-LB Programmer's Console]] (which plugs into an otherwise-standard SPC slot), the CPU and the Programmer's Console do some communication via the backplane. Pins CP1 and CR1 are Halt Request and Halt Grant, respectively; they allow the KY11-B to tell the CPU to halt.
-==See Also==
+==Pinout==
 * [[Modified UNIBUS Device]]
 [[Category: UNIBUS]]

@@ Line 9: / Line 9: @@
 ==Grants==
-SPC slots were wired to bring all 5 UNIBUS [[bus grant line|grant lines]] through the device; this was performed in rows C (for [[Non-Processor Request|NPG]]) and D (for BGx). The device board generally had a header which routed the grant (and matching request) line for the desired priority level to the [[interrupt]] [[circuit]]ry, and passed the other grant lines through.
+SPC slots were wired to bring all 5 UNIBUS [[bus grant line|grant lines]] through the device; this was performed in rows C (for [[Non-Processor Request and Grant|NPG]]) and D (for BGx).
-The DMA (NPG) grant line generally had a jumper on the backplane, which had to be removed if a DMA device was plugged into the slot. Un-occupied slots needed to have either a [[G727 grant continuity card|G727]] or a [[G7273 grant continuity card]] installed.
+The device board generally had a header which routed the grant (and matching request) line for the desired priority level to the [[interrupt]] [[circuit]]ry, and passed the other grant lines through. Un-occupied slots needed to have a [[G727 grant continuity card|G727]] installed.
 ==SPC Extensions==

@@ Line 1: / Line 1: @@
 '''Small Peripheral Controller''' or '''SPC''' was [[DEC]]'s name for a board slot in the [[backplane]]s of [[UNIBUS]] [[PDP-11]]s into which small [[device controller]]s, etc, could be plugged. It was a [[DEC card form factor|quad]]-high slot, occupying [[DEC edge connector contact identification|rows C-F]] in a hex slot.
-It was originally conceived to hold a dual-height device-specific card, along with single-height [[M105 Address Selector]] and [[M782 Interrupt Control]] [[FLIP CHIP]]s (later, the M7820 and M7821 revisions). (The known dual-width controllers which did this were the [[KL11 asynchronous serial line interface‎|KL11]] (M780), the [[PC11 High-Speed Paper-Tape Reader/Punch Control|PC11]] (M781), and the  [[DR11-A parallel interface|DR11-A]] (M786).)
+It was originally conceived to hold a dual-height device-specific card, along with single-height [[M105 Address Selector]] and [[M782 Interrupt Control]] [[FLIP CHIP]]s (later, the M7820 and M7821 revisions). (Among the dual-width controllers which did this were the [[KL11 asynchronous serial line interface‎|KL11]] (M780), the [[PC11 High-Speed Paper-Tape Reader/Punch Control|PC11]] (M781), the [[DR11-A parallel interface|DR11-A]] (M786), and the [[CR11 Controller|CR11]] (M829).)
 The appropriate UNIBUS signal lines ([[address]], data, etc) were thus wired to the appropriate rows/pins in SPC slots. Other pins were wired to allow the necessary communication between the cards, without requiring cables between them.

@@ Line 17: / Line 17: @@
 On some systems, some SPC pins were recycled for other purposes.
-In the [[PDP-11/04]] and [[PDP-11/34]], on the [[DD11-P backplane]] which holds the [[Cenral Processing Unit|CPU]] card(s), along with the [[KY11-LB Programmer's Console]] (which plugs into an otherwise-standard SPC slot), the CPU and the Programmer's Console do some communication via the backplane. Pins CP1 and CR1 are Halt Request and Halt Grant, respectively; they allow the KY11-B to tell the CPU to halt.
+In the [[PDP-11/04]] and [[PDP-11/34]], on the [[DD11-P backplane]] which holds the [[Central Processing Unit|CPU]] card(s), along with the [[KY11-LB Programmer's Console]] (which plugs into an otherwise-standard SPC slot), the CPU and the Programmer's Console do some communication via the backplane. Pins CP1 and CR1 are Halt Request and Halt Grant, respectively; they allow the KY11-B to tell the CPU to halt.
 ==See Also==

@@ Line 1: / Line 1: @@
-'''Small Peripheral Controller''' or '''SPC''' was [[DEC]]'s name for an I/O board slot in the [[backplane]]s of [[UNIBUS]] [[PDP-11]]s. It was a [[DEC card form factor|quad]] slot, occupying [[DEC edge connector contact identification|rows C-F]] in a hex slot, and could hold any kind of device.
+'''Small Peripheral Controller''' or '''SPC''' was [[DEC]]'s name for a board slot in the [[backplane]]s of [[UNIBUS]] [[PDP-11]]s into which small [[device controller]]s, etc, could be plugged. It was a [[DEC card form factor|quad]]-high slot, occupying [[DEC edge connector contact identification|rows C-F]] in a hex slot.
-It was originally conceived to hold a dual-height device-specific card, along with single-height M105 Address Selector and [[M782 Interrupt Control]] [[FLIP CHIP]]s (later, the M7820 and M7821 revisions). The appropriate UNIBUS signal lines ([[address]], data, etc) were thus wired to the appropriate rows/pins in SPC slots. Other pins were wired to allow the necessary communication between the cards, without requiring cables between them.
+It was originally conceived to hold a dual-height device-specific card, along with single-height [[M105 Address Selector]] and [[M782 Interrupt Control]] [[FLIP CHIP]]s (later, the M7820 and M7821 revisions). (The known dual-width controllers which did this were the [[KL11 asynchronous serial line interface‎|KL11]] (M780), the [[PC11 High-Speed Paper-Tape Reader/Punch Control|PC11]] (M781), and the  [[DR11-A parallel interface|DR11-A]] (M786).)
 It soon became more cost-effective to fabricate an entire device on a single quad card, but the pinout was retained. (For the pinout of an SPC slot, see [[UNIBUS#Pinout|here]].)
@@ Line 15: / Line 17: @@
 On some systems, some SPC pins were recycled for other purposes.
-In the [[PDP-11/04]] and [[PDP-11/34]], on the backplane which holds the [[CPU]] card(s), along with the [[KY11-LB Programmer's Console]], the [[Central Processing Unit|CPU]] and the Programmer's Console do some communication via the backplane. Pins CP1 and CR1 are Halt Request and Halt Grant, respectively; they allow the KY11-B to tell the CPU to halt.
+In the [[PDP-11/04]] and [[PDP-11/34]], on the backplane which holds the [[Cenral Processing Unit|CPU]] card(s), along with the [[KY11-LB Programmer's Console]] (which plugs into an otherwise-standard SPC slot), the CPU and the Programmer's Console do some communication via the backplane. Pins CP1 and CR1 are Halt Request and Halt Grant, respectively; they allow the KY11-B to tell the CPU to halt.
 ==See Also==

← Older revision		Revision as of 20:58, 17 November 2018
Line 21:		Line 21:
	* [[Modified UNIBUS Device]]		* [[Modified UNIBUS Device]]

−	[[Category: ~~DEC Buses~~]]	+	[[Category: UNIBUS]]