Superscalar - Revision history

Jnc: Undo revision 24128 - already referred

2021-09-09T20:56:29Z

Undo revision 24128 - already referred

← Older revision		Revision as of 20:56, 9 September 2021
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	* [[Out-of-order execution]]		* [[Out-of-order execution]]
	* [[Register renaming]]

	{{semi-stub}}		{{semi-stub}}

	[[Category: CPU Hardware]]		[[Category: CPU Hardware]]

Jnc: /* See also */ +1

2021-09-09T20:55:20Z

Jnc: New cat - not a basic

2018-12-15T14:03:42Z

New cat - not a basic

← Older revision		Revision as of 14:03, 15 December 2018
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	[[Category: CPU ~~Basics‎‎~~]]		[[Category: CPU Hardware]]

Jnc: better cat

2018-12-14T21:56:11Z

better cat

← Older revision		Revision as of 21:56, 14 December 2018
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	[[Category: ~~Hardware~~ Basics‎‎]]		[[Category: CPU Basics‎‎]]

Jnc: +cat

2018-12-13T03:11:41Z

+cat

← Older revision		Revision as of 03:11, 13 December 2018
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	{{semi-stub}}		{{semi-stub}}

			[[Category: Hardware Basics‎‎]]

Jnc: rm dup

2018-12-04T23:08:07Z

rm dup

← Older revision		Revision as of 23:08, 4 December 2018
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	* The system may elect to move the handling out of hardware, and into [[software]]; the [[compiler]] will only issue instruction sequences in which conflicts do not occur.		* The system may elect to move the handling out of hardware, and into [[software]]; the [[compiler]] will only issue instruction sequences in which conflicts do not occur.

	~~The first machine to have a superscalar CPU was the [[CDC 6600]].~~

	==See also==		==See also==

Jnc: ref CDC6600

2018-12-04T19:50:42Z

ref CDC6600

← Older revision		Revision as of 19:50, 4 December 2018
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	Synchronization between the units is an issue; if the Nth instruction in a stream uses an output of the N-1th instruction, the later instruction cannot start until the earlier one has completed. This conflict usually arises over [[register]]s in the CPU. A number of approaches have been used to handle this:		Synchronization between the units is an issue; if the Nth instruction in a stream uses an output of the N-1th instruction, the later instruction cannot start until the earlier one has completed. This conflict usually arises over [[register]]s in the CPU. A number of approaches have been used to handle this:

	* The CPU can include [[hardware]] which looks for these conflicts and 'stalls' the later instruction until the earlier has completed.		* The CPU can include [[hardware]] which looks for these conflicts and 'stalls' the later instruction until the earlier has completed; this was the technique used by the [[CDC 6600]], the first superscalar CPU.

	* When a later instruction needs a register which is used by an earlier instruction, but does not need the ''data'' in the register, a technique called [[register renaming]] is used to allow the later one to start as soon as its input data is available, but using a different physical register.		* When a later instruction needs a register which is used by an earlier instruction, but does not need the ''data'' in the register, a technique called [[register renaming]] is used to allow the later one to start as soon as its input data is available, but using a different physical register.

Jnc: typo, clarify

2018-11-02T12:29:46Z

typo, clarify

← Older revision		Revision as of 12:29, 2 November 2018
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	* The CPU can include [[hardware]] which looks for these conflicts and 'stalls' the later instruction until the earlier has completed.		* The CPU can include [[hardware]] which looks for these conflicts and 'stalls' the later instruction until the earlier has completed.

	* When a later instruction needs a register which is used by an earlier instruction, but does not need the ''data'' in the register, a technique called [[register renaming]] is used to allow the later one to start as its input data is available.		* When a later instruction needs a register which is used by an earlier instruction, but does not need the ''data'' in the register, a technique called [[register renaming]] is used to allow the later one to start as soon as its input data is available, but using a different physical register.

	* The system may elect to move the handling out of hardware, and into [[software]]; the [[compiler]] will only issue instruction sequences in which conflicts do not occur.		* The system may elect to move the handling out of hardware, and into [[software]]; the [[compiler]] will only issue instruction sequences in which conflicts do not occur.

Jnc: A pretty good start

2018-11-01T12:22:21Z

A pretty good start

New page

A '''superscalar''' [[Central Processing Unit|CPU]] [[architecture]] is one which has more than one [[logic]] unit which can perform the computations called for by [[instruction]]s, and which is prepared to 'issue' instructions to more than one of these units simultaneously.

The units may include duplicates (e.g. two [[floating point]] multiplication units), as well as disparate units.

Synchronization between the units is an issue; if the Nth instruction in a stream uses an output of the N-1th instruction, the later instruction cannot start until the earlier one has completed. This conflict usually arises over [[register]]s in the CPU. A number of approaches have been used to handle this:

* The CPU can include [[hardware]] which looks for these conflicts and 'stalls' the later instruction until the earlier has completed.

* When a later instruction needs a register which is used by an earlier instruction, but does not need the ''data'' in the register, a technique called [[register renaming]] is used to allow the later one to start as its input data is available.

* The system may elect to move the handling out of hardware, and into [[software]]; the [[compiler]] will only issue instruction sequences in which conflicts do not occur.

The first machine to have a superscalar CPU was the [[CDC 6600]].

==See also==

* [[Out-of-order execution]]

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← Older revision		Revision as of 20:55, 9 September 2021
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	* [[Out-of-order execution]]		* [[Out-of-order execution]]
			* [[Register renaming]]

	{{semi-stub}}		{{semi-stub}}

	[[Category: CPU Hardware]]		[[Category: CPU Hardware]]