Synchronizer - Revision history

Jnc: grammar

2022-12-01T14:10:32Z

grammar

← Older revision		Revision as of 14:10, 1 December 2022
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	* an [[asynchronous]] circuit.		* an [[asynchronous]] circuit.

	[[Signal]]s which pass across the boundary must be handled in such a way that they reliably appear to the circuitry inside the destination clock domain to be in one state or another. If the incoming signal, and the clock in the destination clock domain are aligned 'just right' (in other words, 'just wrong'), resulting in a [[race]], ~~which~~ can produce [[meta-stability]] issues.		[[Signal]]s which pass across the boundary must be handled in such a way that they reliably appear to the circuitry inside the destination clock domain to be in one state or another. If the incoming signal and the clock in the destination clock domain are aligned 'just right' (in other words, 'just wrong'), resulting in a [[race]], that can produce [[meta-stability]] issues.

	Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.		Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.

Jnc: link to new page

2020-02-12T14:08:08Z

link to new page

← Older revision		Revision as of 14:08, 12 February 2020
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	* an [[asynchronous]] circuit.		* an [[asynchronous]] circuit.

	[[Signal]]s which pass across the boundary must be handled in such a way that they reliably appear to the circuitry inside the destination clock domain to be in one state or another. If the incoming signal, and the clock in the destination clock domain are aligned 'just right' (in other words, 'just wrong'), ~~this process~~ can ~~be subject to~~ [[meta-stability]] issues.		[[Signal]]s which pass across the boundary must be handled in such a way that they reliably appear to the circuitry inside the destination clock domain to be in one state or another. If the incoming signal, and the clock in the destination clock domain are aligned 'just right' (in other words, 'just wrong'), resulting in a [[race]], which can produce [[meta-stability]] issues.

	Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.		Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.

Jnc: bold target

2020-02-06T05:03:08Z

bold target

← Older revision		Revision as of 05:03, 6 February 2020
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	A '''synchronizer''' is a device which interfaces between a block of [[synchronous]] circuity (such a block of circuitry, all using a common [[clock]], forms a so-called 'clock domain'), and an input from either:		A '''synchronizer''' is a device which interfaces between a block of [[synchronous]] circuity (such a block of circuitry, all using a common [[clock]], forms a so-called '''clock domain'''), and an input from either:

	* another block of [[synchronous]] circuitry, but using a clock which is not fixed relative to that of the destination (receiving) clock domain; or		* another block of synchronous circuitry, but using a clock which is not fixed relative to that of the destination (receiving) clock domain; or
	* an [[asynchronous]] circuit.		* an [[asynchronous]] circuit.

Jnc: +cat

2018-12-14T19:59:47Z

+cat

← Older revision		Revision as of 19:59, 14 December 2018
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	* Steve Golson, "''Synchronization and Metastability''", '2014 Synopsys Users Group Conference: SNUG Silicon Valley 2014', 2014 - Contains an excellent description of the problem		* Steve Golson, "''Synchronization and Metastability''", '2014 Synopsys Users Group Conference: SNUG Silicon Valley 2014', 2014 - Contains an excellent description of the problem
	* Ran Ginosar, "''Fourteen Ways to Fool Your Synchronizer''", 'ASYNC '03: Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems', 2003, pp. 89-96 - An interesting discussion of synchronizers and synchronizer issues		* Ran Ginosar, "''Fourteen Ways to Fool Your Synchronizer''", 'ASYNC '03: Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems', 2003, pp. 89-96 - An interesting discussion of synchronizers and synchronizer issues

			[[Category: Hardware Basics]]

Jnc: +links

2018-11-26T01:09:00Z

+links

← Older revision		Revision as of 01:09, 26 November 2018
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	A '''synchronizer''' is a device which interfaces between a block of [[synchronous]] circuity (such a block of circuitry, all using a common clock, forms a so-called 'clock domain'), and an input from either:		A '''synchronizer''' is a device which interfaces between a block of [[synchronous]] circuity (such a block of circuitry, all using a common [[clock]], forms a so-called 'clock domain'), and an input from either:

	* another block of synchronous circuitry, but using a clock which is not fixed relative to that of the destination (receiving) clock domain; or		* another block of [[synchronous]] circuitry, but using a clock which is not fixed relative to that of the destination (receiving) clock domain; or
	* an [[asynchronous]] circuit.		* an [[asynchronous]] circuit.

	~~Signals~~ which pass across the boundary must be handled in such a way that they reliably appear to the circuitry inside the destination clock domain to be in one state or another. If the incoming signal, and the clock in the destination clock domain are aligned 'just right' (in other words, 'just wrong'), this process can be subject to [[meta-stability]] issues.		[[Signal]]s which pass across the boundary must be handled in such a way that they reliably appear to the circuitry inside the destination clock domain to be in one state or another. If the incoming signal, and the clock in the destination clock domain are aligned 'just right' (in other words, 'just wrong'), this process can be subject to [[meta-stability]] issues.

	Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.		Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.
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	At a higher level, a synchronizer should result in a bit string passed across a clock domain boundary being the same on both sides.		At a higher level, a synchronizer should result in a bit string passed across a clock domain boundary being the same on both sides.

	One common way to implement a synchronizer is with two [[flip-~~flops~~]] in series, driven by a common clock from the destination clock domain. This allows the signal from the first flop (which is effectively 'sampling' the input) an entire clock period to settle out from any potential meta-stability, before it is passed on by the second flop; it does however mean that the signal undergoes significant real-time delay.		One common way to implement a synchronizer is with two [[flip-flop]]s in series, driven by a common clock from the destination clock domain. This allows the signal from the first flop (which is effectively 'sampling' the input) an entire clock period to settle out from any potential meta-stability, before it is passed on by the second flop; it does however mean that the signal undergoes significant [[real-time]] delay.

	It is possible to describe a synchronizer as an [[arbiter]] where one of the input signals to the arbiter is the clock of the destination clock domain.		It is possible to describe a synchronizer as an [[arbiter]] where one of the input signals to the arbiter is the clock of the destination clock domain.

Jnc: clarify two-flop clock source

2016-12-03T16:55:20Z

clarify two-flop clock source

← Older revision		Revision as of 16:55, 3 December 2016
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	Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.		Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.

	~~(Interesting question: if such a signal is passed to two ''different'' clock domains in parallel, it appears to be possible to have one see it as '0', whilst the other sees it as '1'.)~~

	At a higher level, a synchronizer should result in a bit string passed across a clock domain boundary being the same on both sides.		At a higher level, a synchronizer should result in a bit string passed across a clock domain boundary being the same on both sides.

	One common way to implement a synchronizer is with two [[flip-flops]] in series, driven by a common clock. This allows the signal from the first flop (which is effectively 'sampling' the input) an entire clock period to settle out from any potential meta-stability, before it is passed on by the second flop; it does however mean that the signal undergoes significant real-time delay.		One common way to implement a synchronizer is with two [[flip-flops]] in series, driven by a common clock from the destination clock domain. This allows the signal from the first flop (which is effectively 'sampling' the input) an entire clock period to settle out from any potential meta-stability, before it is passed on by the second flop; it does however mean that the signal undergoes significant real-time delay.

	It is possible to describe a synchronizer as an [[arbiter]] where one of the input signals to the arbiter is the clock of the destination clock domain.		It is possible to describe a synchronizer as an [[arbiter]] where one of the input signals to the arbiter is the clock of the destination clock domain.

Jnc: /* Further reading */ one more good one

2016-12-02T19:18:54Z

Jnc: Various improvements

2016-12-02T19:13:23Z

Various improvements

← Older revision		Revision as of 19:13, 2 December 2016
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	A '''synchronizer''' is a device which interfaces between ~~two groups~~ of circuitry ~~which are~~ either:		A '''synchronizer''' is a device which interfaces between a block of [[synchronous]] circuity (such a block of circuitry, all using a common clock, forms a so-called 'clock domain'), and an input from either:

	* ~~both [[~~synchronous]], but using ~~clocks~~ which ~~are~~ not fixed relative to ~~one another~~; or		* another block of synchronous circuitry, but using a clock which is not fixed relative to that of the destination (receiving) clock domain; or
	* ~~at least one of the two is~~ [[asynchronous]].		* an [[asynchronous]] circuit.

	~~(A group of circuity all using~~ a ~~common~~ clock ~~forms a so-called '~~clock domain'.)		Signals which pass across the boundary must be handled in such a way that they reliably appear to the circuitry inside the destination clock domain to be in one state or another. If the incoming signal, and the clock in the destination clock domain are aligned 'just right' (in other words, 'just wrong'), this process can be subject to [[meta-stability]] issues.

	~~Signals which pass across the boundary must be handled~~ in ~~such a way that they reliably appear to be~~ in one ~~state or another,~~ to the ~~circuitry inside~~ the ~~destination clock domain~~.		Note that if an incoming signal is passed through two synchronizers in parallel (for use in differing parts of the same clock domain), it is entirely possible for one synchronizer to decide that the signal was a '0', and the other a '1'; such designs should therefore be avoided.

	~~If the incoming~~ signal~~, and the~~ clock in ~~the destination clock domain are aligned~~ '~~just right~~' ~~(in~~ other ~~words,~~ '~~just wrong~~')~~, this process can be subject to [[meta-stability]] issues.~~		(Interesting question: if such a signal is passed to two ''different'' clock domains in parallel, it appears to be possible to have one see it as '0', whilst the other sees it as '1'.)

	At a higher level, a bit string ~~passing~~ across a clock domain boundary ~~must be~~ the same on both sides.		At a higher level, a synchronizer should result in a bit string passed across a clock domain boundary being the same on both sides.

			One common way to implement a synchronizer is with two [[flip-flops]] in series, driven by a common clock. This allows the signal from the first flop (which is effectively 'sampling' the input) an entire clock period to settle out from any potential meta-stability, before it is passed on by the second flop; it does however mean that the signal undergoes significant real-time delay.

			It is possible to describe a synchronizer as an [[arbiter]] where one of the input signals to the arbiter is the clock of the destination clock domain.

			==Further reading==

			* Ran Ginosar, "''Fourteen Ways to Fool Your Synchronizer''", 'ASYNC '03: Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems', 2003, pp. 89-96 - An interesting discussion of synchronizers and synchronizer issues

Jnc: A decent start

2016-12-02T14:15:31Z

A decent start

New page

A '''synchronizer''' is a device which interfaces between two groups of circuitry which are either:

* both [[synchronous]], but using clocks which are not fixed relative to one another; or
* at least one of the two is [[asynchronous]].

(A group of circuity all using a common clock forms a so-called 'clock domain'.)

Signals which pass across the boundary must be handled in such a way that they reliably appear to be in one state or another, to the circuitry inside the destination clock domain.

If the incoming signal, and the clock in the destination clock domain are aligned 'just right' (in other words, 'just wrong'), this process can be subject to [[meta-stability]] issues.

At a higher level, a bit string passing across a clock domain boundary must be the same on both sides.

← Older revision		Revision as of 19:18, 2 December 2016
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	==Further reading==		==Further reading==

			* Steve Golson, "''Synchronization and Metastability''", '2014 Synopsys Users Group Conference: SNUG Silicon Valley 2014', 2014 - Contains an excellent description of the problem
	* Ran Ginosar, "''Fourteen Ways to Fool Your Synchronizer''", 'ASYNC '03: Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems', 2003, pp. 89-96 - An interesting discussion of synchronizers and synchronizer issues		* Ran Ginosar, "''Fourteen Ways to Fool Your Synchronizer''", 'ASYNC '03: Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems', 2003, pp. 89-96 - An interesting discussion of synchronizers and synchronizer issues