Synchronous Backplane Interconnect - Revision history

Jnc: List adapters and devices which can be connected to the SBI

2024-05-14T15:09:49Z

List adapters and devices which can be connected to the SBI

Jnc: More accurate new category

2024-05-07T23:46:06Z

More accurate new category

Jnc: /* External links */ +also in the VHH

2023-03-17T21:01:16Z

‎External links: +also in the VHH

Jnc: /* External links */ +docs

2023-03-17T18:17:59Z

‎External links: +docs

Vaxorcist: Added SBI VAX models

2022-05-25T06:34:17Z

Added SBI VAX models

Jnc: An OK start

2022-01-13T23:48:56Z

An OK start

New page

The '''Synchronous Backplane Interconnect''' (sometimes given as the acronym, '''SBI''') was the high-speed bus which connected the major functional units ([[Central Processing Unit|CPU]], [[main memory]], [[Input/output|I/O]] adapters, etc), in early [[VAX]]en.

It was synchronous, in that everything on the bus happened in fixed time slots; but it was somewhat asynchronous, in that the slots which were part of an operation (e.g. requesting a read; and the data being returned) had no fixed temporal relationship. The slots of different operations may be interleaved; e.g. after a memory read is started in one slot, some other operation might use some of the slots before the one in which the data is returned.

Allocation of slots was done by a fully-distributed arbitration process, among all the functional units attached to the SBI (called 'nexi'). The arbitration is overlaid, temporally, with operation: the selection of which nexus will perform an operation in a following slot is done during the previous slot; during that previous slot, some other operation may have happened. A nexus can be classified as being one of:

* Commander - a nexus that transmits an [[address]] and command
* Responder - a nexus that recognizes an address and responds to the accompanying command
* Transmitter - a nexus that drives the SBI lines
* Receiver - a nexus that examines the SBI lines

Obviously, a nexus may appear in different categories over time; e.g. a CPU is a transmitter during a write to memory, and a receiver during a red.

The SBI has 32 data lines, and 28 address lines (addresses name long-words). It can transfer units of 8, 16, 32 ('long-word'), and 64 ('quad-word') bits. Data is protected by [[parity]] on the SBI.

In addition to data transfer operations, [[interrupt]] operations are also supported.

[[Category: DEC Buses]]
[[Category: VAXen]]

@@ Line 1: / Line 1: @@
-The '''Synchronous Backplane Interconnect''' (sometimes given as the acronym, '''SBI''') was the high-speed bus which connected the major functional units ([[Central Processing Unit|CPU]], [[main memory]], [[Input/output|I/O]] adapters, etc), in early [[VAX]]en:
+The '''Synchronous Backplane Interconnect''' (sometimes given as the acronym, '''SBI''') was the high-speed [[bus]] which connected the major functional units ([[Central Processing Unit|CPU]], [[main memory]], [[Input/output|I/O]] adapters, etc), in early [[VAX]] systems:
 * [[VAX-11/780]]
 * [[VAX-11/782]]
 * [[VAX-11/785]]
 * [[VAX 8600]]
 * [[VAX 8650]]
 It was synchronous, in that everything on the bus happened in fixed time slots; but it was somewhat asynchronous, in that the slots which were part of an operation (e.g. requesting a read; and the data being returned) had no fixed temporal relationship. The slots of different operations may be interleaved; e.g. after a memory read is started in one slot, some other operation might use some of the slots before the one in which the data is returned.
-Allocation of slots was done by a fully-distributed arbitration process, among all the functional units attached to the SBI (called 'nexi'). The arbitration is overlaid, temporally, with operation: the selection of which nexus will perform an operation in a following slot is done during the previous slot; during that previous slot, some other operation may have happened. A nexus can be classified as being one of:
+Allocation of time slots was done by a fully-distributed arbitration process, among all the functional units attached to the SBI (called 'nexi'). The arbitration is overlaid, temporally, with operation: the selection of which nexus will perform an operation in a following slot is done during the previous slot; during that previous slot, some other operation may have happened. A nexus can be classified as being one of:
 * Commander - a nexus that transmits an [[address]] and command
@@ Line 21: / Line 26: @@
 In addition to data transfer operations, [[interrupt]] operations are also supported.
 ==External links==
@@ Line 29: / Line 48: @@
 [[Category: VAX Buses]]

← Older revision		Revision as of 23:46, 7 May 2024
Line 28:		Line 28:
	* [http://www.bitsavers.org/pdf/dec/vax/handbook/VAX_Hardware_Handbook_Volume_1_1986.pdf VAX Hardware Handbook Volume 1] - the SBI is covered in detail in Chapter 9 (pp. 321-344 of the PDF)		* [http://www.bitsavers.org/pdf/dec/vax/handbook/VAX_Hardware_Handbook_Volume_1_1986.pdf VAX Hardware Handbook Volume 1] - the SBI is covered in detail in Chapter 9 (pp. 321-344 of the PDF)

−	[[Category: ~~DEC~~ Buses]]	+	[[Category: VAX Buses]]
−	~~[[Category: VAXen~~]]

@@ Line 26: / Line 26: @@
 * [http://www.bitsavers.org/pdf/dec/vax/780/EK-11780-UG-001_VAX-11_780_Hardware_Users_Guide_197902.pdf VAX-11/780 Hardware User's Guide] (EK-11780-UG-001) - the SBI is covered in Section 1.3.2.1, pp. 21-22 of the PDF
 * [http://www.bitsavers.org/pdf/dec/vax/780/EK-MM780-TD-001_Translation_Buffer_and_Cache_and_SBI_Control_Technical_Description_197804.pdf Translation Buffer, Cache and SBI Control Technical Description] (EK-MM780-TD-001) - the SBI is covered in Section 1.8.1, pp. 29-31 of the PDF, and Section 2.3, pp. 72-129
 [[Category: DEC Buses]]
 [[Category: VAXen]]

← Older revision		Revision as of 06:34, 25 May 2022
Line 1:		Line 1:
−	The '''Synchronous Backplane Interconnect''' (sometimes given as the acronym, '''SBI''') was the high-speed bus which connected the major functional units ([[Central Processing Unit\|CPU]], [[main memory]], [[Input/output\|I/O]] adapters, etc), in early [[VAX]]en.	+	The '''Synchronous Backplane Interconnect''' (sometimes given as the acronym, '''SBI''') was the high-speed bus which connected the major functional units ([[Central Processing Unit\|CPU]], [[main memory]], [[Input/output\|I/O]] adapters, etc), in early [[VAX]]en:
		+
		+	* [[VAX-11/780]]
		+	* [[VAX-11/782]]
		+	* [[VAX-11/785]]
		+	* [[VAX 8600]]
		+	* [[VAX 8650]]

	It was synchronous, in that everything on the bus happened in fixed time slots; but it was somewhat asynchronous, in that the slots which were part of an operation (e.g. requesting a read; and the data being returned) had no fixed temporal relationship. The slots of different operations may be interleaved; e.g. after a memory read is started in one slot, some other operation might use some of the slots before the one in which the data is returned.		It was synchronous, in that everything on the bus happened in fixed time slots; but it was somewhat asynchronous, in that the slots which were part of an operation (e.g. requesting a read; and the data being returned) had no fixed temporal relationship. The slots of different operations may be interleaved; e.g. after a memory read is started in one slot, some other operation might use some of the slots before the one in which the data is returned.