Synchronous Data Link Control - Revision history

Jnc: More - a lot more - on top of the framing

2022-05-29T07:57:30Z

More - a lot more - on top of the framing

← Older revision		Revision as of 07:57, 29 May 2022
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	The checksum covers the address, control and data fields. The frame is followed either by i) another frame, or ii) the idle pattern - back-to-back flags (with the trailing '0' bit of one flag overlaid with the starting '0' bit of the next flag).		The checksum covers the address, control and data fields. The frame is followed either by i) another frame, or ii) the idle pattern - back-to-back flags (with the trailing '0' bit of one flag overlaid with the starting '0' bit of the next flag).

			On top of that, there is an entire other complex layer of protocol, using various values in the 'Control' field: initialization, testing, station identification, configuration, etc. (See the SDLC documentation for more.)

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Jnc: Jnc moved page SDLC to Synchronous Data Link Control: Full name

2022-05-28T17:19:26Z

Jnc moved page SDLC to Synchronous Data Link Control: Full name

← Older revision	Revision as of 17:19, 28 May 2022
(No difference)

Jnc: Covers the basics

2022-05-28T17:18:50Z

Covers the basics

New page

'''Synchronous Data Link Control''' (usually abbreviated to '''SDLC''') is a [[protocol]] used to transmit [[packet]]s over [[synchronous serial line]]s. It can operate over both [[half-duplex]] and [[full-duplex]] links; supported configurations include both point-point and [[multi-point]]. The later protocol [[‎High-Level Data Link Control|HDLC]] is based on SDLC.

SDLC sends 8-bit bytes only. The start and end of the packet (named a 'frame' in SDLC terminology) are marked by a specific bit pattern, '01111110', the 'flag'. Instances of that pattern in the user data are obscured by [[bit stuffing]] - '11111' is replaced, during transmission, by '111110'; the inserted '0' is removed on reception.

If the link does not provide an independent received [[clock]], SDLC uses [[Non Return to Zero Inverted|NRZI]] encoding, to ensure that enough transitions are present to keep the clock synchronized. With NRZI, the bit stuffing used when the data contains long runs of '1' bits provides enough transitions.

An SDLC frame contains these fields:

* Flag - 8 bits
* Address - 8 bits
* Control - 8 bits
* Data - Variable number of 8-bit bytes
* [[Checksum]] - 16 bits

The checksum covers the address, control and data fields. The frame is followed either by i) another frame, or ii) the idle pattern - back-to-back flags (with the trailing '0' bit of one flag overlaid with the starting '0' bit of the next flag).

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==External links==

* [http://www.bitsavers.org/pdf/ibm/datacomm/GA27-3093-2_SDLC_General_Information_Mar79.pdf IBM Synchronous Data Link Control: General Information]

[[Category: Serial Lines]]