T-11 chip - Revision history

Jnc: /* Further reading */ +Using the Falcon SBC-11/21 in a Standalone Environment

2024-08-01T00:05:41Z

‎Further reading: +Using the Falcon SBC-11/21 in a Standalone Environment

Jnc: Avoid dab

2022-09-20T00:27:52Z

Avoid dab

Jnc: /* See also */ +lost img

2022-04-11T06:34:49Z

‎See also: +lost img

Jnc: full formal name, copyedit

2021-03-29T10:15:18Z

full formal name, copyedit

Jnc: An OK start

2021-03-29T01:33:38Z

An OK start

New page

[[Image:0DCT11.jpg|250px|thumb|right|T-11 chip]]

The '''T-11 chip''' (formally the '''DCT11''', although [[Digital Equipment Corporation|DEC]] documentation generally used 'T-11') was a [[microprocessor]] implementation of the [[PDP-11 architecture]] in a single [[integrated circuit|chip]]. Volume production commenced in early 1982.

The T-11 chip implemented a subset of the PDP-11 architecture; it had neither [[memory management]], nor [[floating point]], and it omitted the little-used MARK [[instruction]]. It was primarily intended for use in [[embedded system]]s, but was also used in the [[KXT11]] [[QBUS]] [[Central Processing Unit|CPU]] [[printed circuit board|boards]].

It was a 40-pin [[Dual Inline Package|DIP]] [[NMOS]] chip. It produced all the control outputs needed to directly drive [[Dynamic RAM|DRAM]] [[main memory]] chips; 4K, 16K and 64K parts were all supported. It could also perform [[refresh]] of the DRAM. A configuration [[register]], loaded at power-on, supported both 8-bit and 16-bit wide busses. It needed +5V power only, and all of its [[signal]]s were [[transistor-transistor logic|TTL]]-compatible.

==Chip versions==

There are three versions: two from DEC, [[DEC part number]] 21-17311-01, which operates at a maximum [[clock]] frequency of 7.5 MHz, and the 21-17311-02 which operates at a maximum frequency of 10 MHz; and the 21-17311-00 from a second source, Synertek, also a 7.5 MHz part. All versions are marked "310ES".

==External links==

* [http://www.bitsavers.org/pdf/dec/pdp11/t11/T11_UsersMan.pdf μ/T-11 User's Guide]
* [http://www.bitsavers.org/pdf/dec/pdp11/t11/T11_Engineering_Specification_Rev_E_Mar82.pdf T-11 Engineering Specification]
* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 361-411

{{PDP-11}}

[[Category:PDP-11 Processors]]

← Older revision		Revision as of 00:05, 1 August 2024
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	* [[:File:1DCT11.jpg\|Another T-11]]		* [[:File:1DCT11.jpg\|Another T-11]]
		+
		+	==Further reading==
		+
		+	* ''Using the Falcon SBC-11/21 in a Standalone Environment'', [[MicroNote]] #109
		+	* ''MUL, DIV, and ASH Instruction for the Falcon SBC-l1/21'', MicroNote #110

	==External links==		==External links==

@@ Line 5: / Line 5: @@
 The T-11 implemented a subset of the PDP-11 architecture; it had neither [[memory management]], nor [[floating point]], and it omitted the little-used MARK [[instruction]].
-It was a single 40-pin [[Dual Inline Package|DIP]] [[NMOS]] [[integrated circuit|chip]]. It produced all the control outputs needed to directly drive [[Dynamic RAM|DRAM]] [[main memory]] chips; 4K, 16K and 64K parts were all supported. It could also perform [[refresh]] of the DRAM. A configuration [[register]], loaded at power-on, supported both 8-bit and 16-bit wide busses (along with other options). It needed +5V power only, and all of its [[signal]]s were [[transistor-transistor logic|TTL]]-compatible.
+It was a single 40-pin [[Dual Inline Package|DIP]] [[NMOS]] [[integrated circuit|chip]]. It produced all the control outputs needed to directly drive [[Dynamic RAM|DRAM]] [[main memory]] chips; 4K, 16K and 64K parts were all supported. It could also perform [[memory refresh]] of the DRAM. A configuration [[register]], loaded at power-on, supported both 8-bit and 16-bit wide busses (along with other options). It needed +5V power only, and all of its [[signal]]s were [[transistor-transistor logic|TTL]]-compatible.
 ==Chip versions==

← Older revision		Revision as of 06:34, 11 April 2022
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	{{semi-stub}}		{{semi-stub}}
		+
		+	==See also==
		+
		+	* [[:File:1DCT11.jpg\|Another T-11]]

	==External links==		==External links==

@@ Line 1: / Line 1: @@
 [[Image:0DCT11.jpg|250px|thumb|right|T-11 chip]]
-The '''T-11 chip''' (formally the '''DCT11''', although [[Digital Equipment Corporation|DEC]] documentation generally used 'T-11') was a [[microprocessor]] implementation of the [[PDP-11 architecture]] in a single [[integrated circuit|chip]]. Volume production commenced in early 1982.
+The '''T-11 chip''' (formally the '''DCT11-AA''', although most [[Digital Equipment Corporation|DEC]] documentation used 'T-11') was a [[microprocessor]] implementation of the [[PDP-11 architecture]]. It was primarily intended for use in [[embedded system]]s, but was also used in the [[KXT11]] [[QBUS]] [[Central Processing Unit|CPU]] [[printed circuit board|boards]]. Volume production commenced in early 1982.
-The T-11 chip implemented a subset of the PDP-11 architecture; it had neither [[memory management]], nor [[floating point]], and it omitted the little-used MARK [[instruction]]. It was primarily intended for use in [[embedded system]]s, but was also used in the [[KXT11]] [[QBUS]] [[Central Processing Unit|CPU]] [[printed circuit board|boards]].
+The T-11 implemented a subset of the PDP-11 architecture; it had neither [[memory management]], nor [[floating point]], and it omitted the little-used MARK [[instruction]].
-It was a 40-pin [[Dual Inline Package|DIP]] [[NMOS]] chip. It produced all the control outputs needed to directly drive [[Dynamic RAM|DRAM]] [[main memory]] chips; 4K, 16K and 64K parts were all supported. It could also perform [[refresh]] of the DRAM. A configuration [[register]], loaded at power-on, supported both 8-bit and 16-bit wide busses. It needed +5V power only, and all of its [[signal]]s were [[transistor-transistor logic|TTL]]-compatible.
+It was a single 40-pin [[Dual Inline Package|DIP]] [[NMOS]] [[integrated circuit|chip]]. It produced all the control outputs needed to directly drive [[Dynamic RAM|DRAM]] [[main memory]] chips; 4K, 16K and 64K parts were all supported. It could also perform [[refresh]] of the DRAM. A configuration [[register]], loaded at power-on, supported both 8-bit and 16-bit wide busses (along with other options). It needed +5V power only, and all of its [[signal]]s were [[transistor-transistor logic|TTL]]-compatible.
 ==Chip versions==
 There are three versions: two from DEC, [[DEC part number]] 21-17311-01, which operates at a maximum [[clock]] frequency of 7.5 MHz, and the 21-17311-02 which operates at a maximum frequency of 10 MHz; and the 21-17311-00 from a second source, Synertek, also a 7.5 MHz part. All versions are marked "310ES".
 ==External links==