Talk:KL10 - Revision history

Jnc: /* S-Bus/X-Bus differences */ typo

2024-04-03T10:17:17Z

‎S-Bus/X-Bus differences: typo

Jnc: /* Front end backplanes */ new section

2024-04-02T22:03:50Z

‎Front end backplanes: new section

Larsbrinkhoff: Go wild!

2023-11-13T17:12:01Z

Go wild!

Jnc: /* Optional cache */ Source for '5' number

2023-11-13T15:59:59Z

‎Optional cache: Source for '5' number

Jnc: /* Optional cache */ new section

2023-11-13T12:35:14Z

‎Optional cache: new section

Larsbrinkhoff: OZ configuration

2023-11-13T06:28:47Z

OZ configuration

Jnc: /* Clock speed */ Apparently more than one clock tick per uprocessor cycle

2023-11-12T15:11:09Z

‎Clock speed: Apparently more than one clock tick per uprocessor cycle

Larsbrinkhoff: /* Clock speed */ I had it 25/30 MHz for some unknown reason.

2023-11-12T14:09:48Z

‎Clock speed: I had it 25/30 MHz for some unknown reason.

Jnc: /* Clock speed */ new section

2023-11-12T13:56:27Z

‎Clock speed: new section

Larsbrinkhoff: /* TENEX */ Confimed by 2xJames.

2022-08-18T06:04:25Z

‎TENEX: Confimed by 2xJames.

@@ Line 54: / Line 54: @@
 == S-Bus/X-Bus differences ==
-So I've been reading the MF20 Technical Manual, and in section 1.1.2.4, "KL10 CPU Nodifications" (pg. 1-4) it says:
+So I've been reading the MF20 Technical Manual, and in section 1.1.2.4, "KL10 CPU Modifications" (pg. 1-4) it says:
 ''uses an improved version of the KL10's SBus called the XBus .. the M8519 SBus translator modules in slots 7 and 8 of the CPU backplane must be replaced ..''

← Older revision		Revision as of 22:03, 2 April 2024
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	: Sure, why not! [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 18:12, 13 November 2023 (CET)		: Sure, why not! [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 18:12, 13 November 2023 (CET)
		+
		+	== Front end backplanes ==
		+
		+	The backplanes in the KL10 front end shown [https://www.cca.org/tech/rcs/pdp-11-40/ here] are (in the image that shows the pin side of the backplanes, from the left):
		+
		+	* [[KD11-A CPU]] (9-slot)
		+	* [[MM11-U core memory]] (9-slot)
		+	* [[RH11 MASSBUS controller]] (9-slot)
		+	* 2 * [[DD11-C backplane]] (4-slot)
		+
		+	The first 3 are probably a standard set; not sure about the DD11-C's. MIT-MC's included at least one [[DH11 asynchronous serial line interface\|DH11]]. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 00:03, 3 April 2024 (CEST)

← Older revision		Revision as of 17:12, 13 November 2023
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	Should we have an MCA20 page which explains this? It would be pretty easy to do - most of the content is already here! :-) [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 13:35, 13 November 2023 (CET)		Should we have an MCA20 page which explains this? It would be pretty easy to do - most of the content is already here! :-) [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 13:35, 13 November 2023 (CET)
		+
		+	: Sure, why not! [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 18:12, 13 November 2023 (CET)

@@ Line 126: / Line 126: @@
 The 'Channel' probably refers to the CBus, needed for the RH20. There is no 'No Channel no Cache' column in that table; I wonder if that configuration ''couldn't'' work (I can't offhand see why it wouldn't, but I have not studied the issue), or just that they didn't offer it?
-The reason I didn't think the MCA20 could be optional is because there are actually two completely separate caches in the KL (actually, [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-OKL10-TM_KL10_TechRef_Aug84.pdf KL10 Tech Manual] says there are ''four'' - in A.1 - but I have no idea what the other two are) - the 'main memory' cache (used for instructions, operands, etc) and the 'paging' cache (used for page table entries). The MCA25 replaces them ''both'', so I assumed that the MCA20 contains them both, too - which would make it effectively non-optional - because without the cached page table entries, each paged memory reference would take several memory cycles (ISTR the number I read somewhere is five, but I can only think of three: the UPT pointer to the page table, the page table entry, and then the actual memory reference) cutting the effective memory bandwidth by 2/3, which is clearly unreasonable. The answer is that the MCA20 ''only'' contains the 'main memory' cache (although I have to confirm that by looking at KL10 MBox prints to confirm that the 'paging' cache is there).
+The reason I didn't think the MCA20 could be optional is because there are actually two completely separate caches in the KL (actually, [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-OKL10-TM_KL10_TechRef_Aug84.pdf KL10 Tech Manual] says there are ''four'' - in A.1 - but I have no idea what the other two are) - the 'main memory' cache (used for instructions, operands, etc) and the 'paging' cache (used for page table entries). The MCA25 replaces them ''both'', so I assumed that the MCA20 contains them both, too - which would make it effectively non-optional - because without the cached page table entries, each paged memory reference would take several memory cycles (the KL10 TM says five - Section A.3 - but I can only think of three: the UPT pointer to the page table, the page table entry, and then the actual memory reference) cutting the effective memory bandwidth by 5/6, which is clearly unreasonable. The answer is that the MCA20 contains the 'main memory' cache ''only'' (although I have to confirm that by looking at KL10 MBox prints to confirm that the 'paging' cache is there).
 Should we have an MCA20 page which explains this? It would be pretty easy to do - most of the content is already here! :-) [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 13:35, 13 November 2023 (CET)

← Older revision		Revision as of 12:35, 13 November 2023
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	machine could be up for use by Lab members who want to test it out in		machine could be up for use by Lab members who want to test it out in
	2 or 3 weeks.		2 or 3 weeks.
		+
		+	== Optional cache ==
		+
		+	There are a variety of sources that indicate that the original KL cache (the MCA20) was optional; I was somewhat dubious about that (below), but it turns out it's true: the [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP00267_MCA20_Nov76.pdf MCA20 Field Maintenance Print Set] has a 'Module Location Chart' on pg. 3 which has a "Channel no Cache" column. So I guess it's correct - one apparently really could get a KL10-C without a cache!
		+
		+	The 'Channel' probably refers to the CBus, needed for the RH20. There is no 'No Channel no Cache' column in that table; I wonder if that configuration ''couldn't'' work (I can't offhand see why it wouldn't, but I have not studied the issue), or just that they didn't offer it?
		+
		+	The reason I didn't think the MCA20 could be optional is because there are actually two completely separate caches in the KL (actually, [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-OKL10-TM_KL10_TechRef_Aug84.pdf KL10 Tech Manual] says there are ''four'' - in A.1 - but I have no idea what the other two are) - the 'main memory' cache (used for instructions, operands, etc) and the 'paging' cache (used for page table entries). The MCA25 replaces them ''both'', so I assumed that the MCA20 contains them both, too - which would make it effectively non-optional - because without the cached page table entries, each paged memory reference would take several memory cycles (ISTR the number I read somewhere is five, but I can only think of three: the UPT pointer to the page table, the page table entry, and then the actual memory reference) cutting the effective memory bandwidth by 2/3, which is clearly unreasonable. The answer is that the MCA20 ''only'' contains the 'main memory' cache (although I have to confirm that by looking at KL10 MBox prints to confirm that the 'paging' cache is there).
		+
		+	Should we have an MCA20 page which explains this? It would be pretty easy to do - most of the content is already here! :-) [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 13:35, 13 November 2023 (CET)

← Older revision		Revision as of 06:28, 13 November 2023
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	:: I wonder if that 50 MHz means that it does one uinstruction every 20 nsec, or does the uprocessor use more than one clock cycle per uinst? That could explain that factor-of-two difference. I'm not up for studying the [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-OKL10-TM_KL10_TechRef_Aug84.pdf KL10 Tech manual] to work out the answer, though! It ''does'' say (Section 3.2.1.1) "30 MHz clock to the MBox, a 12.5 MHz clock to the EBox control store", which makes it sound like the uprocessor does not run at the full clock rate. That might be your answer. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 16:10, 12 November 2023 (CET)		:: I wonder if that 50 MHz means that it does one uinstruction every 20 nsec, or does the uprocessor use more than one clock cycle per uinst? That could explain that factor-of-two difference. I'm not up for studying the [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-OKL10-TM_KL10_TechRef_Aug84.pdf KL10 Tech manual] to work out the answer, though! It ''does'' say (Section 3.2.1.1) "30 MHz clock to the MBox, a 12.5 MHz clock to the EBox control store", which makes it sound like the uprocessor does not run at the full clock rate. That might be your answer. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 16:10, 12 November 2023 (CET)
		+
		+	== OZ configuration ==
		+
		+	Date: 21 March 1982 03:09-EST
		+	From: Xxxxxx Xxxxx Xxxxxx <XXXX at MIT-AI>
		+	Subject: (current-state-of-OZ?)
		+	To: BUG-OZ at MIT-AI
		+
		+	[...]
		+
		+	As many people have noticed, OZ has arrived. The configuration is as
		+	follows:
		+
		+	8 RP06 disk drives, 176 megabytes per drive.
		+	2 TU77 tape drives. 1600 bpi maximum density.
		+	(We hope to get a 6250 bpi tape drive, because backing up our disks
		+	would require too much tape otherwise)
		+	1 DecSystem 2060. Comes in 4 cabinets; I/O, Front End, CPU, and
		+	External Memory Cabinet.
		+	1 DN20 for terminal interface.
		+	1 AN20 for Arpanet interace.
		+
		+	The electricians should be done about next Tuesday; DEC could probably
		+	come next Wednesday and begin installation. I would suspect that the
		+	machine could be up for use by Lab members who want to test it out in
		+	2 or 3 weeks.

← Older revision		Revision as of 15:11, 12 November 2023
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	: Interesting, I got 25/30 MHz in http://pdp10.nocrew.org/cpu/processors.html, but since I wrote that decades ago I don't know the source. [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 15:09, 12 November 2023 (CET)		: Interesting, I got 25/30 MHz in http://pdp10.nocrew.org/cpu/processors.html, but since I wrote that decades ago I don't know the source. [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 15:09, 12 November 2023 (CET)
		+
		+	:: I wonder if that 50 MHz means that it does one uinstruction every 20 nsec, or does the uprocessor use more than one clock cycle per uinst? That could explain that factor-of-two difference. I'm not up for studying the [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-OKL10-TM_KL10_TechRef_Aug84.pdf KL10 Tech manual] to work out the answer, though! It ''does'' say (Section 3.2.1.1) "30 MHz clock to the MBox, a 12.5 MHz clock to the EBox control store", which makes it sound like the uprocessor does not run at the full clock rate. That might be your answer. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 16:10, 12 November 2023 (CET)

← Older revision		Revision as of 14:09, 12 November 2023
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	So [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-0KL10-02_KL10MaintHbk/EK-0KL10-02_part1.pdf EK-0KL10-02] says "KL10-PV - A KL10-PA which has been modified to include extended addressing, more extensive microcode, and a faster clock". The info block only lists a single clock speed. I went looking, and in [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-1080U-SD-003_1080_1090_SysDescr_Jan77.pdf EK-1080U-SD-003], which I am currently mining for useful stuff, I find (pg. SYS1/4-10) "master clock which runs at 50 MHz in the model A CPU and 58 MHz in the model B CPU" (blast, that PFDF doesn't include OCR; had to type the quotation). Eureka! [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:56, 12 November 2023 (CET)		So [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-0KL10-02_KL10MaintHbk/EK-0KL10-02_part1.pdf EK-0KL10-02] says "KL10-PV - A KL10-PA which has been modified to include extended addressing, more extensive microcode, and a faster clock". The info block only lists a single clock speed. I went looking, and in [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-1080U-SD-003_1080_1090_SysDescr_Jan77.pdf EK-1080U-SD-003], which I am currently mining for useful stuff, I find (pg. SYS1/4-10) "master clock which runs at 50 MHz in the model A CPU and 58 MHz in the model B CPU" (blast, that PFDF doesn't include OCR; had to type the quotation). Eureka! [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:56, 12 November 2023 (CET)
		+
		+	: Interesting, I got 25/30 MHz in http://pdp10.nocrew.org/cpu/processors.html, but since I wrote that decades ago I don't know the source. [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 15:09, 12 November 2023 (CET)

← Older revision		Revision as of 13:56, 12 November 2023
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	:: I also contacted former USC staff James Pepin and James Wiedel, who confirmed ECL ran TENEX on a KL10 (and a KI10 before that). [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 08:04, 18 August 2022 (CEST)		:: I also contacted former USC staff James Pepin and James Wiedel, who confirmed ECL ran TENEX on a KL10 (and a KI10 before that). [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 08:04, 18 August 2022 (CEST)
		+
		+	== Clock speed ==
		+
		+	So [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-0KL10-02_KL10MaintHbk/EK-0KL10-02_part1.pdf EK-0KL10-02] says "KL10-PV - A KL10-PA which has been modified to include extended addressing, more extensive microcode, and a faster clock". The info block only lists a single clock speed. I went looking, and in [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-1080U-SD-003_1080_1090_SysDescr_Jan77.pdf EK-1080U-SD-003], which I am currently mining for useful stuff, I find (pg. SYS1/4-10) "master clock which runs at 50 MHz in the model A CPU and 58 MHz in the model B CPU" (blast, that PFDF doesn't include OCR; had to type the quotation). Eureka! [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:56, 12 November 2023 (CET)

← Older revision		Revision as of 06:04, 18 August 2022
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	: What I was kind of fishing for was whether there really was a KL10 TENEX at all, out in the wild outside DEC. But now I found an Arpanet Resources Handbook from 1978 that clearly says USC-ECL was a KL10 running TENEX, so that's settled. [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 14:13, 28 March 2022 (CEST)		: What I was kind of fishing for was whether there really was a KL10 TENEX at all, out in the wild outside DEC. But now I found an Arpanet Resources Handbook from 1978 that clearly says USC-ECL was a KL10 running TENEX, so that's settled. [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 14:13, 28 March 2022 (CEST)
		+
		+	:: I also contacted former USC staff James Pepin and James Wiedel, who confirmed ECL ran TENEX on a KL10 (and a KI10 before that). [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 08:04, 18 August 2022 (CEST)