Talk:LSI-11 - Revision history

Larsbrinkhoff: /* Microcode width */ Thanks!

2018-03-26T20:21:36Z

‎Microcode width: Thanks!

Jnc: clarify

2018-03-25T17:36:28Z

clarify

Jnc: /* Microcode width */ Yes, extra functions; uROM address mystery?

2018-03-25T13:06:29Z

‎Microcode width: Yes, extra functions; uROM address mystery?

Jnc: /* Microcode width */ Typo

2018-03-25T12:29:12Z

‎Microcode width: Typo

Jnc: /* Microcode width */ Maybe they control other stuff?

2018-03-25T12:28:46Z

‎Microcode width: Maybe they control other stuff?

Larsbrinkhoff: 22 vs 16 bit wide ROM?

2018-03-25T09:16:00Z

22 vs 16 bit wide ROM?

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Question: How come the microcode ROMs are 22 bits wide, yet the opcodes are 16 bits wide? (AS documented in the WP16/CP1600 manuals.) [[User:Larsbrinkhoff|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff|talk]]) 11:16, 25 March 2018 (CEST)

← Older revision		Revision as of 20:21, 26 March 2018
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	: Yes, that's exactly what they do. There are 4 bits (MIB18-21) which are a 3-bit code, and an 'enable' bit (see section 4.2.2.7 'Special Control Functions' in the LSI-11 manual EK-LSI11-TM-003). When the latter is high, the other three are run into a 3->8 decoder to generate a bunch of special control signals.		: Yes, that's exactly what they do. There are 4 bits (MIB18-21) which are a 3-bit code, and an 'enable' bit (see section 4.2.2.7 'Special Control Functions' in the LSI-11 manual EK-LSI11-TM-003). When the latter is high, the other three are run into a 3->8 decoder to generate a bunch of special control signals.
	: The thing I'm puzzled by, looking at the prints, is that the uROMs don't seem to have address input pins? There are Micro Instruction Bus (WMIB) pins 1-21, 4 clock phases, a uROM disable ... and that's it! The WMIB must be a dual-function (address and data) bus, and therefore tri-state (read by the uROM chips during the address phase, and driven by them during the data phase). [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 15:06, 25 March 2018 (CEST)		: The thing I'm puzzled by, looking at the prints, is that the uROMs don't seem to have address input pins? There are Micro Instruction Bus (WMIB) pins 1-21, 4 clock phases, a uROM disable ... and that's it! The WMIB must be a dual-function (address and data) bus, and therefore tri-state (read by the uROM chips during the address phase, and driven by them during the data phase). [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 15:06, 25 March 2018 (CEST)
		+
		+	:: Thanks a lot! I think it would be intersting to make an interpreter for the uROM. [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 22:21, 26 March 2018 (CEST)

← Older revision		Revision as of 17:36, 25 March 2018
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	: Yes, that's exactly what they do. There are 4 bits (MIB18-21) which are a 3-bit code, and an 'enable' bit (see section 4.2.2.7 'Special Control Functions' in the LSI-11 manual EK-LSI11-TM-003). When the latter is high, the other three are run into a 3->8 decoder to generate a bunch of special control signals.		: Yes, that's exactly what they do. There are 4 bits (MIB18-21) which are a 3-bit code, and an 'enable' bit (see section 4.2.2.7 'Special Control Functions' in the LSI-11 manual EK-LSI11-TM-003). When the latter is high, the other three are run into a 3->8 decoder to generate a bunch of special control signals.
−	: The thing I'm puzzled by, looking at the prints, is that the uROMs don't seem to have address input pins? There are Micro Instruction Bus (WMIB) pins 1-21, 4 clock phases, a uROM disable ... and that's it! The WMIB must be a dual-function (address and data), and therefore tri-state (read by the uROM chips during the address phase, and driven by them during the data phase) ~~bus~~. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 15:06, 25 March 2018 (CEST)	+	: The thing I'm puzzled by, looking at the prints, is that the uROMs don't seem to have address input pins? There are Micro Instruction Bus (WMIB) pins 1-21, 4 clock phases, a uROM disable ... and that's it! The WMIB must be a dual-function (address and data) bus, and therefore tri-state (read by the uROM chips during the address phase, and driven by them during the data phase). [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 15:06, 25 March 2018 (CEST)

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	: Just a guess, but it is ''microcode''; some of the other bits may control other stuff on the board? The prints probably say (they are available for both the dual- and quad-width LSI-11 CPU cards. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:28, 25 March 2018 (CEST)		: Just a guess, but it is ''microcode''; some of the other bits may control other stuff on the board? The prints probably say (they are available for both the dual- and quad-width LSI-11 CPU cards. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:28, 25 March 2018 (CEST)
		+
		+	: Yes, that's exactly what they do. There are 4 bits (MIB18-21) which are a 3-bit code, and an 'enable' bit (see section 4.2.2.7 'Special Control Functions' in the LSI-11 manual EK-LSI11-TM-003). When the latter is high, the other three are run into a 3->8 decoder to generate a bunch of special control signals.
		+	: The thing I'm puzzled by, looking at the prints, is that the uROMs don't seem to have address input pins? There are Micro Instruction Bus (WMIB) pins 1-21, 4 clock phases, a uROM disable ... and that's it! The WMIB must be a dual-function (address and data), and therefore tri-state (read by the uROM chips during the address phase, and driven by them during the data phase) bus. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 15:06, 25 March 2018 (CEST)

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-====
+==Microcode width==
 Question: How come the microcode ROMs are 22 bits wide, yet the opcodes are 16 bits wide? (AS documented in the WP16/CP1600 manuals.) [[User:Larsbrinkhoff|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff|talk]]) 11:16, 25 March 2018 (CEST)
 : Just a guess, but it is ''microcode''; some of the other bits may control other stuff on the board? The prints probably say (they are available for both the dual- and quad-width LSI-11 CPU cards. [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 14:28, 25 March 2018 (CEST)

← Older revision		Revision as of 12:28, 25 March 2018
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		+	====
		+
	Question: How come the microcode ROMs are 22 bits wide, yet the opcodes are 16 bits wide? (AS documented in the WP16/CP1600 manuals.) [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 11:16, 25 March 2018 (CEST)		Question: How come the microcode ROMs are 22 bits wide, yet the opcodes are 16 bits wide? (AS documented in the WP16/CP1600 manuals.) [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 11:16, 25 March 2018 (CEST)
		+
		+	: Just a guess, but it is ''microcode''; some of the other bits may control other stuff on the board? The prints probably say (they are available for both the dual- and quad-width LSI-11 CPU cards. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:28, 25 March 2018 (CEST)