Talk:Swapping - Revision history

Jnc: /* Etymology */ Interesting find on the PDP-1 drum with the 'exchange' operation in hardware

2025-05-03T12:57:02Z

‎Etymology: Interesting find on the PDP-1 drum with the 'exchange' operation in hardware

Larsbrinkhoff: /* Etymology */ Clarify.

2025-05-02T10:47:22Z

‎Etymology: Clarify.

Larsbrinkhoff: /* Etymology */ Fredkin style drum swapping?

2025-05-02T10:45:04Z

‎Etymology: Fredkin style drum swapping?

Jnc: /* Etymology */ My long-winded answer

2025-05-01T22:05:49Z

‎Etymology: My long-winded answer

Larsbrinkhoff: /* Etymology */ new section

2025-05-01T13:24:25Z

‎Etymology: new section

New page

== Etymology ==

I have the impression the word "swapping" comes from drum storage, where it was possible to write a memory area to a drum sector, whilst simultaneously reading another sector into ''the same'' area. Thoughts? [[User:Larsbrinkhoff|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff|talk]]) 15:24, 1 May 2025 (CEST)

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	:: The way I imagined this would work was, 1. The swapping would occur during a core memory cycle. As we know, a core memory read is destructive and will need to write back the contents, or some other data. And, 2. the drum would have fixed heads for each track, with the capability for several (i.e. any two) to operate at the same time. (Drums wouldn't normally have moving heads, did they?)		:: The way I imagined this would work was, 1. The swapping would occur during a core memory cycle. As we know, a core memory read is destructive and will need to write back the contents, or some other data. And, 2. the drum would have fixed heads for each track, with the capability for several (i.e. any two) to operate at the same time. (Drums wouldn't normally have moving heads, did they?)
−	:: Searching around, I think I got the idea from a description of Fredkin's PDP-1 swapping timesharing system ~~here. Search for "swap".~~ https://retrocomputingforum.com/t/1963-sperry-rand-univac-fastrand-magnetic-drum/2929 [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 12:45, 2 May 2025 (CEST)	+	:: Searching around, I think I got the idea from a description of Fredkin's PDP-1 swapping timesharing system [https://retrocomputingforum.com/t/1963-sperry-rand-univac-fastrand-magnetic-drum/2929 here]. Search for "swap". [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 12:45, 2 May 2025 (CEST)
		+
		+	::: Yes, ''but''! :-)
		+	::: Good point about core memory; that characteristic was used for 'read/modify/write' cycles on several computers. E.g. on the [[UNIBUS]], it has a 'DATIP' read/modify/write cycle, which was added specifically to support read/modify/write cycles on core memory, on early PDP-11's (like the [[PDP-11/20]]) - for speed only, as a UNIBUS as only a single CPU. Read/modify/write cycles were used in some multi-processor systems, like Multics, for atomic operations, like locking locks. IIRC, some PDP-10's also had a read/modify/write bus cycle.
		+	::: But notice that use/support of it has to be built in at a very low level - and the same would have to be true of use on rotating magnetic media. (The controller would have to know that it was doing an 'exchange' operation, involving two [logically separate] transfers at the same time, intermingled.) You have found one such, on Fredkin's PDP-1 drum; I don't know of any others.
		+	::: Whether that was the source of the term 'swap', I don't know. I guess I'll ask Jerry if he recalls.
		+
		+	::: Some early drums did have moving heads (just as some early disks had fixed heads; see [[Special:WhatLinksHere/Fixed-head_disk\|here]]). The [[DEUCE]] drum, for one, had moving heads. A Web search for 'computer drum moving head' will turn up some discussion of them. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:56, 3 May 2025 (CEST)

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 : If you'd like, I can query Jerry Saltzer about the origin of the term - he lived through the start of that era, as a system programmer on CTSS. [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 00:05, 2 May 2025 (CEST)
-:: The way I imagined this would work was, 1. The swapping would occur during a core memory cycle.  As we know, a core memory read is destructive and will need to write back the contents, or some other data.  And, 2. the drum would have fixed heads for each track.  (Drums wouldn't normally have moving heads, did they?)
+:: The way I imagined this would work was, 1. The swapping would occur during a core memory cycle.  As we know, a core memory read is destructive and will need to write back the contents, or some other data.  And, 2. the drum would have fixed heads for each track, with the capability for several (i.e. any two) to operate at the same time.  (Drums wouldn't normally have moving heads, did they?)
 :: Searching around, I think I got the idea from a description of Fredkin's PDP-1 swapping timesharing system here.  Search for "swap".  https://retrocomputingforum.com/t/1963-sperry-rand-univac-fastrand-magnetic-drum/2929 [[User:Larsbrinkhoff|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff|talk]]) 12:45, 2 May 2025 (CEST)

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	: To get back to your original query, I'm pretty sure the 'swapping' referred to was just 'swapping the use of ''the'' main memory among multiple processes' (remember that CTSS used an 'onion-skin' memory allocation algorithm - i.e. only one process was ever 'swapped in' at a time).		: To get back to your original query, I'm pretty sure the 'swapping' referred to was just 'swapping the use of ''the'' main memory among multiple processes' (remember that CTSS used an 'onion-skin' memory allocation algorithm - i.e. only one process was ever 'swapped in' at a time).
	: If you'd like, I can query Jerry Saltzer about the origin of the term - he lived through the start of that era, as a system programmer on CTSS. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 00:05, 2 May 2025 (CEST)		: If you'd like, I can query Jerry Saltzer about the origin of the term - he lived through the start of that era, as a system programmer on CTSS. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 00:05, 2 May 2025 (CEST)
		+
		+	:: The way I imagined this would work was, 1. The swapping would occur during a core memory cycle. As we know, a core memory read is destructive and will need to write back the contents, or some other data. And, 2. the drum would have fixed heads for each track. (Drums wouldn't normally have moving heads, did they?)
		+	:: Searching around, I think I got the idea from a description of Fredkin's PDP-1 swapping timesharing system here. Search for "swap". https://retrocomputingforum.com/t/1963-sperry-rand-univac-fastrand-magnetic-drum/2929 [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 12:45, 2 May 2025 (CEST)

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	I have the impression the word "swapping" comes from drum storage, where it was possible to write a memory area to a drum sector, whilst simultaneously reading another sector into ''the same'' area. Thoughts? [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 15:24, 1 May 2025 (CEST)		I have the impression the word "swapping" comes from drum storage, where it was possible to write a memory area to a drum sector, whilst simultaneously reading another sector into ''the same'' area. Thoughts? [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 15:24, 1 May 2025 (CEST)
		+
		+	: After thinking about that for a while, I'm not sure that would generally have actually been possible in the hardware. Let me explain my thinking, and you can tell me if/where I have made a mistake. (Yes, yes, I know this opening part isn't an answer to the actual question you asked; I'll get to that at the bottom.)
		+	: First, with most main memory technologies, it's not actually possible to read location X and write location Y ''at the same time''. E.g. with core, to read location 0200, in a 0100x0100 array, one has to 'select' location 0200 by actuating the 02 'X' line and the 0 'Y' line. One obviously can't write location 0301 at the same time. Multi-port memories, presented with two simultaneous requests, usually do first one, and then the other. (See, for example, [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-HIAA-D%20MA10%20Core%20Memory%20Maintenance%20Manual.pdf MA10 Core Memory Maintenance Manual], 3.3 Operational Description: "Priority logic contained within the MA10 is provided to establish the sequence of memory unit access when two or more ports are addressed simultaneously." Section 4.3, Request Logic, gives the operation in detail. Basically, the lower priority port is made to wait until the higher priority port is done.
		+	: Of course, if the reads in your hypothetical query are higher priority (to the main memory) than the writes, that would 'sort of' work - if the sequence of read and write operations are interleaved with each other. But then we get to the second problem - contention for the storage medium.
		+	: If there is only one read/write head, or one set of analog circuitry to drive the head, it can't read ''and'' write two different sectors at the same time. If there are two heads, one connected to read circuitry, and one to write, then there one can write one sector, whilst simultaneously reading another. Some machines (especially those with drum main memories, like the [[Bendix G-15]]), actually did something close to this: 'accumulator' tracks had multiple heads, spaced around the track (with the same data written in all the sections), to minimize access times.
		+	: So, ''in theory'', one could have had a machine which could simultaneously write a memory block to one sector, while reading another sector into the same block - but I don't know of one that had that hardware capability.
		+	: To get back to your original query, I'm pretty sure the 'swapping' referred to was just 'swapping the use of ''the'' main memory among multiple processes' (remember that CTSS used an 'onion-skin' memory allocation algorithm - i.e. only one process was ever 'swapped in' at a time).
		+	: If you'd like, I can query Jerry Saltzer about the origin of the term - he lived through the start of that era, as a system programmer on CTSS. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 00:05, 2 May 2025 (CEST)