Talk:UNIBUS parity - Revision history

Jnc: /* 18-bit MASSBUS tape controllers */ Manual explicitly says "TM03/TU45" supports "18-bit .. data transfers over Unibus"

2025-02-07T12:34:47Z

‎18-bit MASSBUS tape controllers: Manual explicitly says "TM03/TU45" supports "18-bit .. data transfers over Unibus"

Jnc: /* 18-bit MASSBUS tape controllers I am totally stunned

2025-02-07T04:37:57Z

/* 18-bit MASSBUS tape controllers I am totally stunned

Larsbrinkhoff: /* 18-bit mode */ Info from TM03 Users Guide.

2025-02-06T15:29:07Z

‎18-bit mode: Info from TM03 Users Guide.

Jnc: Apparently not...

2019-01-24T02:26:06Z

Apparently not...

Jnc: fmt typo

2019-01-23T20:44:26Z

fmt typo

Jnc: OK, done - and KL10 question

2019-01-23T20:43:10Z

OK, done - and KL10 question

Jnc: /* 18-bit mode */ Good idea

2019-01-23T13:28:32Z

‎18-bit mode: Good idea

Larsbrinkhoff: 18-bit UNIBUS data using parity bits.

2019-01-23T11:40:58Z

18-bit UNIBUS data using parity bits.

New page

Would it be appropriate to mention 18-bit data on the UNIBUS here? I understand the KS10 and some of its devices could use the two parity bits for data. Maybe some of the 18-bit PDPs too? [[User:Larsbrinkhoff|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff|talk]]) 12:40, 23 January 2019 (CET)

← Older revision		Revision as of 12:34, 7 February 2025
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	:* If the latter, was it utilized in 36-bit mode? (I suppose you could look at the code and see.)		:* If the latter, was it utilized in 36-bit mode? (I suppose you could look at the code and see.)
	: Now I need to go back to sleep again! [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 05:37, 7 February 2025 (CET)		: Now I need to go back to sleep again! [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 05:37, 7 February 2025 (CET)
		+
		+	: It would also be good to know if KS10's were usually sold with the PDP-10 version of the TM03.
		+	: [http://www.bitsavers.org/pdf/dec/pdp10/KS10/EK-KS10-TM-PRE_tech_Feb78.pdf EK-KS10-TM-PRE] (and probably other places) says that "'DEC FS' will not maintain systems that do not have TU45 magtape" (pg. 9 of the PDF); that could likely have been because they needed the capability to load 36-bit data (for diagnostics), which would have required the PDP-10 version of the TM03.
		+	: That manual does say (pg. 13) that the "TM03/TU45" supports "18-bit (NPR) data transfers over Unibus". So I guess that answers that.
		+	: Interestingly, that manual does show (pg. 27) a "Typical KS10 System Configuration", with a TU45 attached through a "TM02/TM03"! The "TM02" is printed; the "TM03" is written in by hand! An apparent contradiction between i) no 18-bit support on the TM02, and ii) a need for 18-bit support, perhaps to load diagnostics? (One can imagine all sorts of ways that came to be. A simple error in an early version of the documentation? Someone in FS realized that they needed a way to load 36-bit data, which meant it had to have a TM03?)
		+	: I give up! [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 13:34, 7 February 2025 (CET)

@@ Line 7: / Line 7: @@
 : OK, done - see what you think.
-:: Circling back to this, I checked https://bitsavers.computerhistory.org/pdf/dec/magtape/tm03/TM03_UsersGuide.pdf and on page 2-16 it says it can do 18 and 36 bits.  Page 1-8 talk about the bit fiddler, but doesn't specify how it works with >16 bits.  https://gunkies.org/wiki/TM03_magtape_controller says it can have a "M8915 for use with a PDP-10". [[User:Larsbrinkhoff|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff|talk]]) 16:28, 6 February 2025 (CET)
+:: From looking at some 1080/1090 documentation, access to shared RP disks from the KL10 side was via an RH10/RH20, not via the -11; in any event, I didn't see any indication that DMA cycles on the UNIBUS can do 18-bit cycles to the KL10's memory. [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 03:26, 24 January 2019 (CET)
-: Also, I wonder about the RH11 in the [[KL10]] front end - could it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the [[RH10]] could get too them too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 21:43, 23 January 2019 (CET)
+==18-bit MASSBUS tape controllers==
-:: From looking at some 1080/1090 documentation, access to shared RP disks from the KL10 side was via an RH10/RH20, not via the -11; in any event, I didn't see any indication that DMA cycles on the UNIBUS can do 18-bit cycles to the KL10's memory. [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 03:26, 24 January 2019 (CET)
+: I am totally stunned (absolutely literally - I had to lie down and sleep to recover).

@@ Line 7: / Line 7: @@
 : OK, done - see what you think.
 : Also, I wonder about the RH11 in the [[KL10]] front end - could it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the [[RH10]] could get too them too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 21:43, 23 January 2019 (CET)
 :: From looking at some 1080/1090 documentation, access to shared RP disks from the KL10 side was via an RH10/RH20, not via the -11; in any event, I didn't see any indication that DMA cycles on the UNIBUS can do 18-bit cycles to the KL10's memory. [[User:Jnc|Jnc]] ([[User talk:Jnc|talk]]) 03:26, 24 January 2019 (CET)

← Older revision		Revision as of 02:26, 24 January 2019
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	: OK, done - see what you think.		: OK, done - see what you think.
	: Also, I wonder about the RH11 in the [[KL10]] front end - could it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the [[RH10]] could get too them too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 21:43, 23 January 2019 (CET)		: Also, I wonder about the RH11 in the [[KL10]] front end - could it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the [[RH10]] could get too them too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 21:43, 23 January 2019 (CET)
		+
		+	:: From looking at some 1080/1090 documentation, access to shared RP disks from the KL10 side was via an RH10/RH20, not via the -11; in any event, I didn't see any indication that DMA cycles on the UNIBUS can do 18-bit cycles to the KL10's memory. [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 03:26, 24 January 2019 (CET)

← Older revision		Revision as of 20:44, 23 January 2019
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	: OK, done - see what you think.		: OK, done - see what you think.
−	: Also, I wonder about the RH11 in the [[KL10]] front end - could	+	: Also, I wonder about the RH11 in the [[KL10]] front end - could it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the [[RH10]] could get too them too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 21:43, 23 January 2019 (CET)
−	it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the [[RH10]] could get too them
−	too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 21:43, 23 January 2019 (CET)

← Older revision		Revision as of 20:43, 23 January 2019
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	: Yeah, good idea. This hack is mentioned in a number of places (e.g. [[MX15-B Memory Multiplexer]], [[RH11 MASSBUS controller]], etc). Once I update here, I'll link them in.		: Yeah, good idea. This hack is mentioned in a number of places (e.g. [[MX15-B Memory Multiplexer]], [[RH11 MASSBUS controller]], etc). Once I update here, I'll link them in.
	: I wonder if this possibility was thought of up front, or if this hack was only developed later, when someone had a brainwave? [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:28, 23 January 2019 (CET)		: I wonder if this possibility was thought of up front, or if this hack was only developed later, when someone had a brainwave? [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:28, 23 January 2019 (CET)
		+
		+	: OK, done - see what you think.
		+	: Also, I wonder about the RH11 in the [[KL10]] front end - could
		+	it do 18-bit transfers over the front end's UNIBUS? ISTR that the RP's on that were double ported, and the [[RH10]] could get too them
		+	too, so maybe no need for the 18-bit mode on the front end (and probably not high enough performance anyway). [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 21:43, 23 January 2019 (CET)

← Older revision		Revision as of 13:28, 23 January 2019
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−	Would it be appropriate to mention 18-bit data on the UNIBUS here? I understand the KS10 and some of its devices could use the two parity bits for data. Maybe some of the 18-bit PDPs too? [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 12:40, 23 January 2019 (CET)	+	==18-bit mode==
		+
		+	Would it be appropriate to mention 18-bit data on the UNIBUS here? I understand the KS10 and some of its devices could use the two parity bits for data. Maybe some of the 18-bit PDPs too? [[User:Larsbrinkhoff\|Larsbrinkhoff]] ([[User talk:Larsbrinkhoff\|talk]]) 12:40, 23 January 2019 (CET)
		+
		+	: Yeah, good idea. This hack is mentioned in a number of places (e.g. [[MX15-B Memory Multiplexer]], [[RH11 MASSBUS controller]], etc). Once I update here, I'll link them in.
		+	: I wonder if this possibility was thought of up front, or if this hack was only developed later, when someone had a brainwave? [[User:Jnc\|Jnc]] ([[User talk:Jnc\|talk]]) 14:28, 23 January 2019 (CET)