Three cycle data break - Revision history

Jnc: Actually, now that I think about it, this one is probably better

2022-06-15T20:06:25Z

Actually, now that I think about it, this one is probably better

Jnc: New cat

2022-06-15T17:48:36Z

New cat

Jnc: copyedit, hdw savings details

2021-05-14T11:12:55Z

copyedit, hdw savings details

Jnc: Several DEC machines used this, not just the PDP-8

2021-05-13T23:32:43Z

Several DEC machines used this, not just the PDP-8

Jnc: Redir - Covered there

2020-05-09T20:15:30Z

Redir - Covered there

New page

#Redirect [[OMNIBUS]]

← Older revision		Revision as of 20:06, 15 June 2022
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	This moved some of the replicated [[logic]] needed to implement the I/O devices (such as the [[gate]]s needed to maintain the buffer information [[register]]s) from each I/O device into one shared set within the processor, thereby economizing on the hardware in the device. (Recall that this mechanism was used in an era when gates were constructed out of individual physical [[transistor]]s; [[integrated circuit]]s were still quite some distance into the future.) The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation).		This moved some of the replicated [[logic]] needed to implement the I/O devices (such as the [[gate]]s needed to maintain the buffer information [[register]]s) from each I/O device into one shared set within the processor, thereby economizing on the hardware in the device. (Recall that this mechanism was used in an era when gates were constructed out of individual physical [[transistor]]s; [[integrated circuit]]s were still quite some distance into the future.) The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation).

−	[[Category: DEC ~~Electrical~~]]	+	[[Category: DEC Buses]]

← Older revision		Revision as of 17:48, 15 June 2022
Line 5:		Line 5:
	This moved some of the replicated [[logic]] needed to implement the I/O devices (such as the [[gate]]s needed to maintain the buffer information [[register]]s) from each I/O device into one shared set within the processor, thereby economizing on the hardware in the device. (Recall that this mechanism was used in an era when gates were constructed out of individual physical [[transistor]]s; [[integrated circuit]]s were still quite some distance into the future.) The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation).		This moved some of the replicated [[logic]] needed to implement the I/O devices (such as the [[gate]]s needed to maintain the buffer information [[register]]s) from each I/O device into one shared set within the processor, thereby economizing on the hardware in the device. (Recall that this mechanism was used in an era when gates were constructed out of individual physical [[transistor]]s; [[integrated circuit]]s were still quite some distance into the future.) The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation).

−	[[Category: DEC ~~Hardware~~]]	+	[[Category: DEC Electrical]]

@@ Line 1: / Line 1: @@
-'''Three cycle data break''' was a form of [[Direct Memory Access|DMA]] to [[main memory]] used on a number of [[List of Programmed Data Processors|early DEC computers]].
+'''Three cycle data break''' was a form of [[Direct Memory Access|DMA]] for high-speed [[peripheral]]s (usually [[mass storage]]) to [[main memory]], used on a number of [[List of Programmed Data Processors|early DEC computers]].
-The [[buffer]] address and word count were kept in main memory (at an [[address]] often specified by [[jumper]]s on the [[peripheral]]). This required the assistance of the [[Central Processing Unit|processor]] to handle the operation, both placing it in charge of actually doing the transfer, and also maintaining the DMA address and word count. In three successive memory cycles, the processor would update the word count, update the transfer address, and finally store or retrieve the actual I/O data word.
+The [[buffer]] address and word count were kept in main memory (at an [[address]] often specified by [[jumper]]s in the peripheral). This required the assistance of the [[Central Processing Unit|processor]] to handle the operation, both placing it in charge of actually doing the transfer, and also maintaining the DMA address and word count. In three successive memory cycles, the processor would update the word count, update the transfer address, and finally store or retrieve the actual I/O data word.
-This moved some of common [[logic]] (needed to implement the I/O device) from each I/O device into one shared set of hardware within the processor, thereby economizing on the hardware in the device. The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation).
+This moved some of the replicated [[logic]] needed to implement the I/O devices (such as the [[gate]]s needed to maintain the buffer information [[register]]s) from each I/O device into one shared set within the processor, thereby economizing on the hardware in the device. (Recall that this mechanism was used in an era when gates were constructed out of individual physical [[transistor]]s; [[integrated circuit]]s were still quite some distance into the future.) The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation).
 [[Category: DEC Hardware]]

← Older revision		Revision as of 23:32, 13 May 2021
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−	~~#Redirect~~ [[~~OMNIBUS~~]]	+	'''Three cycle data break''' was a form of [[Direct Memory Access\|DMA]] to [[main memory]] used on a number of [[List of Programmed Data Processors\|early DEC computers]].
		+
		+	The [[buffer]] address and word count were kept in main memory (at an [[address]] often specified by [[jumper]]s on the [[peripheral]]). This required the assistance of the [[Central Processing Unit\|processor]] to handle the operation, both placing it in charge of actually doing the transfer, and also maintaining the DMA address and word count. In three successive memory cycles, the processor would update the word count, update the transfer address, and finally store or retrieve the actual I/O data word.
		+
		+	This moved some of common [[logic]] (needed to implement the I/O device) from each I/O device into one shared set of hardware within the processor, thereby economizing on the hardware in the device. The downside is that it imposed a greater load on the memory, since each actual data transfer included three memory cycles (one each to read and update the count and address, and one to actually do the operation).
		+
		+	[[Category: DEC Hardware]]