UNIBUS - Revision history

Jnc: /* See also */ +UniBone/QBone

2024-01-14T21:26:50Z

‎See also: +UniBone/QBone

Jnc: Add UNIBUS FLIP CHIPs

2023-11-28T12:02:15Z

Add UNIBUS FLIP CHIPs

Jnc: /* External links */ +A useful early general handbook

2023-11-28T01:57:44Z

‎External links: +A useful early general handbook

Jnc: /* Cables */ clarify

2023-07-19T14:35:28Z

‎Cables: clarify

Jnc: /* External links */ +PDP-11 Bus Technical Description

2023-05-16T18:34:07Z

‎External links: +PDP-11 Bus Technical Description

Jnc: /* See also */ +M8264 No-SACK Timeout Module

2022-12-04T14:31:51Z

‎See also: +M8264 No-SACK Timeout Module

Jnc: /* External links */ typo

2022-10-24T19:46:54Z

‎External links: typo

Jnc: +Category:DEC Documentation Errors‎‎

2022-10-24T19:42:25Z

+Category:DEC Documentation Errors‎‎

Jnc: /* DMA and Interrupts */ +missing word, link

2022-06-05T21:16:43Z

‎DMA and Interrupts: +missing word, link

Jnc: analog design was wired-OR

2022-06-05T14:34:06Z

analog design was wired-OR

@@ Line 286: / Line 286: @@
 * [[DA11-B DMA UNIBUS Link]]
 * [[DA11-F UNIBUS Window]]
 <!-- ==Further reading== -->
 ==External links==

@@ Line 11: / Line 11: @@
 The design deliberately minimized the amount of redundant logic required in the system. For example, a system always contained more slave devices than master devices, so most of the complex logic required to implement asynchronous data transfers was forced into the relatively few master devices. For interrupts, only the ''interrupt-fielding processor'' needed to contain the complicated timing logic. The end result was that most I/O controllers could be implemented with very simple [[logic]]; most of the critical logic was later implemented as a custom [[MSI]] [[integrated circuit|IC]].
-In [[analog]] terms, most of the [[signal]]s of the UNIBUS were [[broadcast]] on [[wired-OR]] [[transmission line]]s.
+In [[analog]] terms, most of the [[signal]]s of the UNIBUS were [[broadcast]] on [[wired-OR]] [[transmission line]]s. Most were held at a low [[voltage]] by the lines' [[terminator]]s when idle; they were then driven to [[ground]] by the transmitter to assert a signal.
 It could exist on a cable (the original physical form of implementation), and later, within a [[backplane]] (in '[[Small Peripheral Controller]] (SPC)' or '[[Modified UNIBUS Device]] (MUD)' slots). Up to approximately 20 nodes (devices) could be connected to a single UNIBUS segment; additional segments could be connected via a [[bus repeater]].
@@ Line 42: / Line 42: @@
 In the final, and lasting version, a slave which stored data along with parity (usually main memory) could indicate to a master, during a DATI/DATIP operation, that there had been a parity error seen when retrieving the data. The master could then take whatever action it deemed appropriate; most PDP-11 CPU's would perform a [[trap]].
-==Documentation==
+==Implementation==
-'''''NOTE:''''' There is a serious editing error in the latter volume, in the description of UNIBUS arbitration. On page 38, immediately after step 13 of the NPR Arbitration Sequence ("13. .... SACK must be negated before BBSY may be negated."), it says "A bus master may issue an interrupt command to the interrupt fielding processor."
+===Lines===
-Despite its location in the text, this does '''''not''''' apply to the "NPR arbitration sequence" being discussed above. There is an editing error - this text is (or ''should be'') separate from the "NPR Arbitration Sequence" section just before it; it belongs with "BR Interrupt Arbitration Sequence" - that header (on pg. 39) was put in the wrong place.
+The UNIBUS is usually described as containing 56 lines. In its initial [[BC11A UNIBUS cable]] instantiation, the UNIBUS was composed of 72 wires (2 standard DEC board edge connectors, with 36 lines per connector); when not counting the power and ground lines, this was reduced to the canonical 56.
 Among the UNIBUS signals are:
@@ Line 253: / Line 245: @@
 |-
 |}
 {{wp-orig}}
@@ Line 277: / Line 292: @@
 * [http://www.bitsavers.org/pdf/dec/unibus/UnibusSpec1979.pdf pdp-11 UNIBUS Design Description]
 * [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_BusHandbook1979.pdf pdp11 bus handbook] (EB-17525-20/79-070-14-55)
-* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_PeripheralsHbk_1972.pdf pdp11 peripherals and interfacing handbook (1972 edition)] - general UNIBUS operation, and [[analog]] description, is covered in Part 2 (pp. 185-242 of the PDF)
+* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_PeripheralsHbk_1972.pdf pdp11 peripherals and interfacing handbook (1972 edition)] - general UNIBUS operation, and [[analog]] description, is covered in Part 2 (pp. 185-216 of the PDF); the UNIBUS FLIP CHIPs are covered in Section 2.2.3 (pp. 216-242 of the PDF)
 * [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_PeripheralsHbk_1976.pdf pdp11 peripherals handbook (1976 edition)] - has a very detailed description of master/slave operations, bus requests and interrupts, in chapter 5, "UNIBUS Theory and Operation"
 * [http://www.bitsavers.org/pdf/dec/pdp11/memos/690402_PDP-11_Uni-Bus.pdf PDP-11 Bus Technical Description] - internal memo describing an earlier design

@@ Line 277: / Line 277: @@
 * [http://www.bitsavers.org/pdf/dec/unibus/UnibusSpec1979.pdf pdp-11 UNIBUS Design Description]
 * [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_BusHandbook1979.pdf pdp11 bus handbook] (EB-17525-20/79-070-14-55)
 * [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_PeripheralsHbk_1976.pdf pdp11 peripherals handbook (1976 edition)] - has a very detailed description of master/slave operations, bus requests and interrupts, in chapter 5, "UNIBUS Theory and Operation"
 * [http://www.bitsavers.org/pdf/dec/pdp11/memos/690402_PDP-11_Uni-Bus.pdf PDP-11 Bus Technical Description] - internal memo describing an earlier design

@@ Line 87: / Line 87: @@
 For many years, the cable used to carry the UNIBUS from one backplane to another was the [[BC11A UNIBUS cable]], a pair of wide (3-3/4 inch) white [[Flexprint cable]]s, separated by a thin foam layer, with small [[printed circuit board]]s with edge connector fingers on each end of the cable. The latter plugged into 'UNIBUS In' and 'UNIBUS out' slots in backplanes. The flat cables actually contained 64 connectors each; every other trace was grounded, to prevent [[cross-talk]] between the signal lines.
-DEC later developed a series of cards (the M9014, an [[DEC card form factor|extended height dual card]], and the M9042 short dual card) which plug into the same slots, and contain three 2x20 [[Berg connector|Berg header]]s for 40-conductor [[flat cable]]s (known as H854 cables in DEC parlance); a pair of these, and three cables, perform the same role as a BC11A cable. Both of these cards use the [[UNIBUS H854 header pinout|same header pinout]], so they may be used interchangeably.
+DEC later developed a series of cards (the M9014, an [[DEC card form factor|extended height dual card]], and the M9042 short dual card) which plug into the same slots, and contain three 2x20 [[Berg connector|Berg header]]s for 40-conductor [[flat cable]]s (known as H854 cables in DEC parlance); a pair of these cards, and three cables, perform the same role as a BC11A cable. Both of these cards use the [[UNIBUS H854 header pinout|same header pinout]], so they may be used interchangeably.
 ===Pinout===

@@ Line 272: / Line 272: @@
 * [[DA11-F UNIBUS Window]]
-<!-- ==Further reading==
+<!-- ==Further reading== -->
 ==External links==
@@ Line 280: / Line 278: @@
 * [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_BusHandbook1979.pdf pdp11 bus handbook] (EB-17525-20/79-070-14-55)
 * [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_PeripheralsHbk_1976.pdf pdp11 peripherals handbook (1976 edition)] - has a very detailed description of master/slave operations, bus requests and interrupts, in chapter 5, "UNIBUS Theory and Operation"
 [[Category: UNIBUS]]
 [[Category: DEC Buses]]
 [[Category: DEC Documentation Errors‎‎]]

@@ Line 261: / Line 261: @@
 * [[UNIBUS Initialization]]
 * [[Bus Arbitration on the Unibus and QBUS]]
 * [[UNIBUS and QBUS termination]]
 * [[UNIBUS Device Addresses]]

← Older revision		Revision as of 19:42, 24 October 2022
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	[[Category: UNIBUS]]		[[Category: UNIBUS]]
	[[Category: DEC Buses]]		[[Category: DEC Buses]]
		+	[[Category:DEC Documentation Errors‎‎]]

@@ Line 32: / Line 32: @@
 Both DMA (in which a device must request control of the bus, so that it can perform a normal master/slave cycle, only with itself as the master), and interrupts, use the same mechanism for the device to communicate with the CPU to request something, and for the CPU to communicate with the device that it has granted the device's request.
-There are [[bus request line]]s (NPR for DMA, and BR4-BR7 for interrupts), and [[bus grant line]]s (NPG for DMA, and BG4-7 for interrupts). The request lines are normal 'wired-OR' broadcast bus lines, but the grant lines are special; they are wired in series - one device's 'grant out' line is connected to the next device's 'grant in' line, starting the CPU's 'grant out' line.
+There are [[bus request line]]s (NPR for DMA, and BR4-BR7 for interrupts), and [[bus grant line]]s (NPG for DMA, and BG4-7 for interrupts). The request lines are normal 'wired-OR' broadcast bus lines, but the grant lines are special; they are wired in series - one device's 'grant out' line is connected to the next device's 'grant in' line, starting with the CPU's 'grant out' line.
-When a device receives a grant, it uses another bus line (SACK) to indicate that it received its grant; if the CPU sends a grant, and does not see a SACK in response, it knows there was some sort of error.
+When a device receives a grant, it uses another bus line (SACK) to indicate that it received its grant; if the CPU sends a grant, and does not see a SACK in response, it knows there was [[M8264 No-SACK Timeout Module#Functionality discussion|some sort of error]].
 ===Parity===