UNIBUS parity - Revision history

Jnc: Add TM03 for magtape support on KS10

2025-02-07T12:45:13Z

Add TM03 for magtape support on KS10

← Older revision		Revision as of 12:45, 7 February 2025
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	The two parity lines, PA and PB, were also taken over to produce an 18 data-[[bit]] wide version of the UNIBUS for use on some of [[Digital Equipment Corporation\|DEC]]'s 18- and 36-bit machines, to allow use of existing [[secondary storage]] [[peripheral\|devices]] and [[device controller]]s on them.		The two parity lines, PA and PB, were also taken over to produce an 18 data-[[bit]] wide version of the UNIBUS for use on some of [[Digital Equipment Corporation\|DEC]]'s 18- and 36-bit machines, to allow use of existing [[secondary storage]] [[peripheral\|devices]] and [[device controller]]s on them.

	The [[MX15-B Memory Multiplexer]] for the [[PDP-15]] would accept 18-bit data over the UNIBUS from a modified controller, e.g. the [[RK11 disk controller#RK11-E\|RK11-E]].		The [[MX15-B Memory Multiplexer]] for the [[PDP-15]] would accept 18-bit data over the UNIBUS from a modified controller, e.g. the [[RK11 disk controller#RK11-E\|RK11-E]]; the [[RH11 MASSBUS controller]] could support 18-bit [[MASSBUS]] devices.

	The UNIBUS Adaptor on the [[KS10]] version of the [[PDP-10]] could also operate in 18-bit mode~~; the [[~~RH11 ~~MASSBUS controller]]~~ there used this to support connection of [[MASSBUS]] [[disk]]s to the KS10 ~~(no~~ [[magnetic tape drive]] ~~system for the UNIBUS is known that~~ supported 18-bit mode operation).		The UNIBUS Adaptor on the [[KS10]] version of the [[PDP-10]] could also operate in 18-bit mode. The RH11's there used this to support connection of 18-bit MASSBUS [[disk]]s to the KS10; the [[TM03 magtape controller]] is the only currently-known way to have a [[magnetic tape drive]] there which supported 18-bit mode operation.

	==History==		==History==

Jnc: /* 18-bit width */ No 18-bit mode magnetic tape drive systems known

2025-02-06T14:48:22Z

18-bit width: No 18-bit mode magnetic tape drive systems known

← Older revision		Revision as of 14:48, 6 February 2025
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	The [[MX15-B Memory Multiplexer]] for the [[PDP-15]] would accept 18-bit data over the UNIBUS from a modified controller, e.g. the [[RK11 disk controller#RK11-E\|RK11-E]].		The [[MX15-B Memory Multiplexer]] for the [[PDP-15]] would accept 18-bit data over the UNIBUS from a modified controller, e.g. the [[RK11 disk controller#RK11-E\|RK11-E]].

	The UNIBUS Adaptor on the [[KS10]] version of the [[PDP-10]] could also operate in 18-bit mode; the [[RH11 MASSBUS controller]] there used this to support connection of [[MASSBUS]] [[disk]]s ~~and~~ [[magnetic tape drive]]~~s to~~ the ~~KS10~~.		The UNIBUS Adaptor on the [[KS10]] version of the [[PDP-10]] could also operate in 18-bit mode; the [[RH11 MASSBUS controller]] there used this to support connection of [[MASSBUS]] [[disk]]s to the KS10 (no [[magnetic tape drive]] system for the UNIBUS is known that supported 18-bit mode operation).

	==History==		==History==

Jnc: /* 18-bit width */ +tapes

2019-11-21T14:54:50Z

18-bit width: +tapes

← Older revision		Revision as of 14:54, 21 November 2019
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	The [[MX15-B Memory Multiplexer]] for the [[PDP-15]] would accept 18-bit data over the UNIBUS from a modified controller, e.g. the [[RK11 disk controller#RK11-E\|RK11-E]].		The [[MX15-B Memory Multiplexer]] for the [[PDP-15]] would accept 18-bit data over the UNIBUS from a modified controller, e.g. the [[RK11 disk controller#RK11-E\|RK11-E]].

	The UNIBUS Adaptor on the [[KS10]] version of the [[PDP-10]] could also operate in 18-bit mode; the [[RH11 MASSBUS controller]] there used this to support connection of [[MASSBUS]] [[disk]]s to the KS10.		The UNIBUS Adaptor on the [[KS10]] version of the [[PDP-10]] could also operate in 18-bit mode; the [[RH11 MASSBUS controller]] there used this to support connection of [[MASSBUS]] [[disk]]s and [[magnetic tape drive]]s to the KS10.

	==History==		==History==

Jnc: /* Second version */ Fastbus only

2019-02-05T15:56:29Z

Second version: Fastbus only

← Older revision		Revision as of 15:56, 5 February 2019
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	===Second version===		===Second version===

	The second version is described in the ''unibus interface manual''. second ~~editioni~~ (DEC-11-HIAB-D).		The second version is described in the ''unibus interface manual''. second edition (DEC-11-HIAB-D).

	There, Table 2-1 has these changed entries for PA and PB: "Parity Bit Low - PA ... Transmits parity bit, low byte" and "Parity Bit High - PB ... Transmits parity bit, high byte"; at the top of page 2-5, the text there is wholly different from the version above, including "These lines are used by the MP11 Parity Option in conjunction with parity memories such as the MM11-FP."		There, Table 2-1 has these changed entries for PA and PB: "Parity Bit Low - PA ... Transmits parity bit, low byte" and "Parity Bit High - PB ... Transmits parity bit, high byte"; at the top of page 2-5, the text there is wholly different from the version above, including "These lines are used by the MP11 Parity Option in conjunction with parity memories such as the MM11-FP."

	This version was apparently actually implemented in the [[MM11-E and MM1-F core memories\|MM11-F]]; in the ''MM11-F Core Memory Manual'' (DEC-11-HMFA-D, on the subject of parity it says (Appendix A - Parity Option): "The data bits on the bus are called BUS DPB0 and BUS DPB1." There is nothing else on how the two parity bits are used, but the clear implication is that the memory just stores them, and hands them to the master over the bus, for actual use.		This version was apparently actually implemented in the [[MM11-E and MM1-F core memories\|MM11-F]]; in the ''MM11-F Core Memory Manual'' (DEC-11-HMFA-D, on the subject of parity it says (Appendix A - Parity Option): "The data bits on the bus are called BUS DPB0 and BUS DPB1." There is nothing else on how the two parity bits are used, but the clear implication is that the memory just stores them, and hands them to the master over the bus, for actual use.

	Another apparent 'tombstone' from this era can be found in the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". It can control, for each 4k block of that section, whether the memory uses odd or even parity - which would be possible with this version of the UNIBUS parity functionality, and e.g. the MM11-F. It is not known whether these registers were actually implemented in an early version of the -11/45, and if so, exactly what functionality was included.

	[[Category: UNIBUS]]		[[Category: UNIBUS]]

Jnc: /* 18-bit width */ grammar

2019-01-24T17:10:15Z

18-bit width: grammar

← Older revision		Revision as of 17:10, 24 January 2019
Line 9:		Line 9:
	The [[MX15-B Memory Multiplexer]] for the [[PDP-15]] would accept 18-bit data over the UNIBUS from a modified controller, e.g. the [[RK11 disk controller#RK11-E\|RK11-E]].		The [[MX15-B Memory Multiplexer]] for the [[PDP-15]] would accept 18-bit data over the UNIBUS from a modified controller, e.g. the [[RK11 disk controller#RK11-E\|RK11-E]].

	The UNIBUS Adaptor on the [[KS10]] version of the [[PDP-10]] could also operate in 18-bit mode; the [[RH11 MASSBUS controller]] used this to support connection of [[MASSBUS]] [[disk]]s to the KS10.		The UNIBUS Adaptor on the [[KS10]] version of the [[PDP-10]] could also operate in 18-bit mode; the [[RH11 MASSBUS controller]] there used this to support connection of [[MASSBUS]] [[disk]]s to the KS10.

	==History==		==History==

Jnc: Add 18-bit mode

2019-01-23T17:53:36Z

Add 18-bit mode

← Older revision		Revision as of 17:53, 23 January 2019
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	'''UNIBUS parity''' has a somewhat complex ~~history~~. The final [[UNIBUS]] spec says [[parity]] implementation is wholly within the slave [[peripheral\|device]], and only an ''error'' [[signal]] is transferred over the [[bus]]. From the ''pdp11 peripherals handbook'', 1975 edition (pg. 5-8): "PA and PB are generated by a slave ... [it] negates PA and asserts PB to indicate a parity error ... both negated indicates no parity error. [other combinations] are conditions reserved for future use."		'''UNIBUS parity''' has a somewhat complex story.

	~~However, originally the~~ UNIBUS parity ~~functionality was planned to be different; sometime around the introduction of~~ the [[~~PDP-11/45~~]], [[~~Digital Equipment Corporation\|DEC~~]] ~~changed~~ it, ~~twice~~.		The final [[UNIBUS]] spec says [[parity]] implementation is wholly within the slave [[peripheral\|device]], and only an ''error'' [[signal]] is transferred over the [[bus]]. From the ''pdp11 peripherals handbook'', 1975 edition (pg. 5-8): "PA and PB are generated by a slave ... [it] negates PA and asserts PB to indicate a parity error ... both negated indicates no parity error. [other combinations] are conditions reserved for future use." However, the original concepts were quite different; see below.

	==First version==		==18-bit width==

			The two parity lines, PA and PB, were also taken over to produce an 18 data-[[bit]] wide version of the UNIBUS for use on some of [[Digital Equipment Corporation\|DEC]]'s 18- and 36-bit machines, to allow use of existing [[secondary storage]] [[peripheral\|devices]] and [[device controller]]s on them.

			The [[MX15-B Memory Multiplexer]] for the [[PDP-15]] would accept 18-bit data over the UNIBUS from a modified controller, e.g. the [[RK11 disk controller#RK11-E\|RK11-E]].

			The UNIBUS Adaptor on the [[KS10]] version of the [[PDP-10]] could also operate in 18-bit mode; the [[RH11 MASSBUS controller]] used this to support connection of [[MASSBUS]] [[disk]]s to the KS10.

			==History==

			Originally the UNIBUS parity functionality was planned to be different; sometime around the introduction of the [[PDP-11/45]], DEC changed it, twice.

			===First version===

	The first version is described in the ''unibus interface manual'', first edition (DEC-11-HIAA-D).		The first version is described in the ''unibus interface manual'', first edition (DEC-11-HIAA-D).
Line 11:		Line 23:
	This first version was not, as far is as known, actually implemented in anything.		This first version was not, as far is as known, actually implemented in anything.

	==Second version==		===Second version===

	The second version is described in the ''unibus interface manual''. second editioni (DEC-11-HIAB-D).		The second version is described in the ''unibus interface manual''. second editioni (DEC-11-HIAB-D).

Jnc: /* Second version */ move parity failure action to KB11-A

2019-01-22T19:29:04Z

Second version: move parity failure action to KB11-A

← Older revision		Revision as of 19:29, 22 January 2019
Line 19:		Line 19:
	This version was apparently actually implemented in the [[MM11-E and MM1-F core memories\|MM11-F]]; in the ''MM11-F Core Memory Manual'' (DEC-11-HMFA-D, on the subject of parity it says (Appendix A - Parity Option): "The data bits on the bus are called BUS DPB0 and BUS DPB1." There is nothing else on how the two parity bits are used, but the clear implication is that the memory just stores them, and hands them to the master over the bus, for actual use.		This version was apparently actually implemented in the [[MM11-E and MM1-F core memories\|MM11-F]]; in the ''MM11-F Core Memory Manual'' (DEC-11-HMFA-D, on the subject of parity it says (Appendix A - Parity Option): "The data bits on the bus are called BUS DPB0 and BUS DPB1." There is nothing else on how the two parity bits are used, but the clear implication is that the memory just stores them, and hands them to the master over the bus, for actual use.

	Another apparent 'tombstone' from this era can be found in the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". ~~One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear~~, ~~the machine will trap to 4!) It also indicates that~~ for each section, ~~it is able to control~~ whether the memory uses odd or even parity - which would be possible with this version of the UNIBUS parity functionality, and e.g. the MM11-F. It is not known whether these registers were actually implemented in an early version of the -11/45, and if so, exactly what functionality was included.		Another apparent 'tombstone' from this era can be found in the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". It can control, for each 4k block of that section, whether the memory uses odd or even parity - which would be possible with this version of the UNIBUS parity functionality, and e.g. the MM11-F. It is not known whether these registers were actually implemented in an early version of the -11/45, and if so, exactly what functionality was included.

	[[Category: UNIBUS]]		[[Category: UNIBUS]]

Jnc: typo

2019-01-22T00:22:22Z

typo

← Older revision		Revision as of 00:22, 22 January 2019
Line 19:		Line 19:
	This version was apparently actually implemented in the [[MM11-E and MM1-F core memories\|MM11-F]]; in the ''MM11-F Core Memory Manual'' (DEC-11-HMFA-D, on the subject of parity it says (Appendix A - Parity Option): "The data bits on the bus are called BUS DPB0 and BUS DPB1." There is nothing else on how the two parity bits are used, but the clear implication is that the memory just stores them, and hands them to the master over the bus, for actual use.		This version was apparently actually implemented in the [[MM11-E and MM1-F core memories\|MM11-F]]; in the ''MM11-F Core Memory Manual'' (DEC-11-HMFA-D, on the subject of parity it says (Appendix A - Parity Option): "The data bits on the bus are called BUS DPB0 and BUS DPB1." There is nothing else on how the two parity bits are used, but the clear implication is that the memory just stores them, and hands them to the master over the bus, for actual use.

	Another apparent 'tombstone' from this era can be found in the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will trap to 4!) It also indicates that for each section, it is able to control whether the memory uses odd or even parity - which would be possible with this version of the UNIBUS parity functionality, and e.g. the MM11-F. It is not known whether these registers were actually implemented in an early version of the -11/45, ~~aand~~ if so, exactly what functionality was included.		Another apparent 'tombstone' from this era can be found in the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will trap to 4!) It also indicates that for each section, it is able to control whether the memory uses odd or even parity - which would be possible with this version of the UNIBUS parity functionality, and e.g. the MM11-F. It is not known whether these registers were actually implemented in an early version of the -11/45, and if so, exactly what functionality was included.

	[[Category: UNIBUS]]		[[Category: UNIBUS]]

Jnc: A new discovery!

2019-01-21T22:23:04Z

A new discovery!

New page

'''UNIBUS parity''' has a somewhat complex history. The final [[UNIBUS]] spec says [[parity]] implementation is wholly within the slave [[peripheral|device]], and only an ''error'' [[signal]] is transferred over the [[bus]]. From the ''pdp11 peripherals handbook'', 1975 edition (pg. 5-8): "PA and PB are generated by a slave ... [it] negates PA and asserts PB to indicate a parity error ... both negated indicates no parity error. [other combinations] are conditions reserved for future use."

However, originally the UNIBUS parity functionality was planned to be different; sometime around the introduction of the [[PDP-11/45]], [[Digital Equipment Corporation|DEC]] changed it, twice.

==First version==

The first version is described in the ''unibus interface manual'', first edition (DEC-11-HIAA-D).

In there, Table 2-1 has these entries for the PA and PB [[conductor|lines]] of the UNIBUS: "Parity Available - PA ... Indicates paritied data" and "Parity Bit - PB ... Transmits parity bit". Also, at the bottom of page 2-4, we find "PA indicates that the data being transferred is to use parity, and PB transmits the parity bit. Neither line is used by the [[KA11 CPU|KA11 processor]]."

This first version was not, as far is as known, actually implemented in anything.

==Second version==

The second version is described in the ''unibus interface manual''. second editioni (DEC-11-HIAB-D).

There, Table 2-1 has these changed entries for PA and PB: "Parity Bit Low - PA ... Transmits parity bit, low byte" and "Parity Bit High - PB ... Transmits parity bit, high byte"; at the top of page 2-5, the text there is wholly different from the version above, including "These lines are used by the MP11 Parity Option in conjunction with parity memories such as the MM11-FP."

This version was apparently actually implemented in the [[MM11-E and MM1-F core memories|MM11-F]]; in the ''MM11-F Core Memory Manual'' (DEC-11-HMFA-D, on the subject of parity it says (Appendix A - Parity Option): "The data bits on the bus are called BUS DPB0 and BUS DPB1." There is nothing else on how the two parity bits are used, but the clear implication is that the memory just stores them, and hands them to the master over the bus, for actual use.

Another apparent 'tombstone' from this era can be found in the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will trap to 4!) It also indicates that for each section, it is able to control whether the memory uses odd or even parity - which would be possible with this version of the UNIBUS parity functionality, and e.g. the MM11-F. It is not known whether these registers were actually implemented in an early version of the -11/45, aand if so, exactly what functionality was included.

[[Category: UNIBUS]]