UNICHANNEL 15 System - Revision history

Jnc: Better cat

2022-11-28T12:48:20Z

Better cat

Jnc: /* External links */ + maint manual, Eng Drwngs

2022-11-26T20:56:11Z

‎External links: + maint manual, Eng Drwngs

Jnc: clarify

2019-12-03T14:46:06Z

clarify

Jnc: +cat

2018-12-19T23:52:16Z

+cat

Jnc: Proper cat

2018-10-21T20:07:03Z

Proper cat

Jnc: spelling

2017-12-10T13:40:01Z

spelling

Jnc: An OK start

2017-12-10T13:29:24Z

An OK start

New page

The '''UNICHANNEL 15 System''' ('''UC15''') is an group of hardware sub-systems which allows a [[PDP-15]] to communicate with a [[PDP-11]] (usually a [[PDP-11/05]]) which acts as an I/O [[front end]], partially to offload the PDP-15's [[Central Processing Unit|CPU]], but also to allow PDP-15 systems access to devices which did not have native PDP-15 support, such as the [[RK05 disk drive]]. The UC15 includes two separate sub-systems:

* An [[MX15-B Memory Multiplexor]], which allows the PDP-11 (both the CPU, and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]].

* A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of [[DR11-C general device interface]] parallel ports, and a [[DR15 Device Interface]].

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← Older revision		Revision as of 12:48, 28 November 2022
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	* [http://bitsavers.org/pdf/dec/pdp15/XVM/UC15_schematics_Aug76.pdf UC15-0 Engineering Drawings]		* [http://bitsavers.org/pdf/dec/pdp15/XVM/UC15_schematics_Aug76.pdf UC15-0 Engineering Drawings]

−	[[Category: ~~DEC Processors~~]]	+	[[Category: PDP-15s]]

← Older revision		Revision as of 20:56, 26 November 2022
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		+	==External links==
		+
		+	* [http://bitsavers.org/pdf/dec/pdp15/XVM/DEC-15-HUCMA-B-D_UC15_Nov73.pdf UC15 unichannel-15 system maintenance manual] (DEC-15-HUCMA-B-D)
		+	* [http://bitsavers.org/pdf/dec/pdp15/XVM/UC15_schematics_Aug76.pdf UC15-0 Engineering Drawings]

	[[Category: DEC Processors]]		[[Category: DEC Processors]]

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 * An [[MX15-B Memory Multiplexer]], which allows the PDP-11 (both the CPU, and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]].
-* A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of [[DR11-C general device interface]] parallel ports, and a [[DR15 Device Interface]].
+* A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of [[DR11-C general device interface]] parallel ports on the PDP-11, and a [[DR15 Device Interface]] on the PDP-15 end.
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 [[Category: DEC Processors]]

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		+	[[Category: DEC Processors]]

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	* A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of [[DR11-C general device interface]] parallel ports, and a [[DR15 Device Interface]].		* A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of [[DR11-C general device interface]] parallel ports, and a [[DR15 Device Interface]].

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 The '''UNICHANNEL 15 System''' ('''UC15''') is an group of hardware sub-systems which allows a [[PDP-15]] to communicate with a [[PDP-11]] (usually a [[PDP-11/05]]) which acts as an I/O [[front end]], partially to offload the PDP-15's [[Central Processing Unit|CPU]], but also to allow PDP-15 systems access to devices which did not have native PDP-15 support, such as the [[RK05 disk drive]]. The UC15 includes two separate sub-systems:
-* An [[MX15-B Memory Multiplexor]], which allows the PDP-11 (both the CPU, and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]].
+* An [[MX15-B Memory Multiplexer]], which allows the PDP-11 (both the CPU, and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]].
 * A data channel between the two CPUs, which allows them to interrupt each other; this channel is implemented with a pair of [[DR11-C general device interface]] parallel ports, and a [[DR15 Device Interface]].
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