VAX 9000 series - Revision history

Jnc: Add new formal group cat

2024-05-20T16:45:22Z

Add new formal group cat

Jnc: Cat rename

2024-05-06T22:45:27Z

Cat rename

Jnc: +New category

2024-01-01T23:26:56Z

+New category

Jnc: New category

2023-12-06T13:11:47Z

New category

Jnc: +Cat

2023-08-13T18:36:11Z

+Cat

Jnc: Target moved to follow VAX article naming system

2023-05-22T17:03:08Z

Target moved to follow VAX article naming system

Jnc: /* Hardware */ cooling

2023-04-01T13:37:58Z

‎Hardware: cooling

Jnc: /* External links */ +AQUARIUS/ARIDUS Preliminary Information Package

2023-04-01T13:36:34Z

‎External links: +AQUARIUS/ARIDUS Preliminary Information Package

Jnc: typos

2023-03-30T17:57:28Z

typos

Jnc: Expand description a bit; + more docs

2023-03-30T12:24:17Z

Expand description a bit; + more docs

← Older revision		Revision as of 16:45, 20 May 2024
Line 38:		Line 38:
	[[Category: VAX Mainframes]]		[[Category: VAX Mainframes]]
	[[Category: VAX Families]]		[[Category: VAX Families]]
		+	[[Category: VAX 9000 Systems]]

@@ Line 1: / Line 1: @@
 The '''VAX 9000 series''' was a high-performance [[VAX]], described by [[Digital Equipment Corporation|DEC]] as a '[[mainframe]] computer'. They were built around a System Control Unit (SCU), which allowed the configuration of tightly-coupled [[multi-processor]]s with up to 4 [[Central Processing Unit|CPUs]]. [[Main memory]] was also connected to the SCU.
-The CPUs were heavily [[pipeline]]d, and were built from [[emitter-coupled logic|ECL]] [[gate array]]s. The performance levels in the line ranged from 30 to 108 [[VUP]]s; the VAX 9000s supported [[vector processing]]. A 'service processor unit' (SPU) containing four [[MicroVAX II]] units acted as a [[front end]]; it was primarily tasked with overseeing the operation of the system, e.g. error detection and recovery.
+The CPUs were heavily [[pipeline]]d, and were built from [[emitter-coupled logic|ECL]] [[gate array]]s. The performance levels in the line ranged from 30 to 108 [[VUP]]s; the VAX 9000s also supported [[vector processing]]. A 'service processor unit' (SPU) containing four [[MicroVAX II]] units acted as a [[front end]]; it was primarily tasked with overseeing the operation of the system, e.g. error detection and recovery.
 The VAX 9000 used the [[Extended Memory Interconnect|XMI]] as its [[input/output|I/O]] [[bus]]; up to 4 were possible in the largest systems. Models in the series included:
@@ Line 13: / Line 13: @@
 ** [[VAX 9000 model 440]] - quadruple-CPU
-The 200 group and the 400 group differ primarily in their physical packaging and available configurations.
+The 2x0 group and the 4x0 group differ primarily in their physical packaging and available configurations.
 [[Operating system]]s offered for them included [[VMS]] and [[Ultrix]] ([[VAXELN]] was supported only on the SPU).
@@ Line 36: / Line 36: @@
 {{Nav VAX}}
-[[Category: Mainframe VAX Computers]]
+[[Category: VAX Mainframes]]
 [[Category: VAX Families]]

← Older revision		Revision as of 23:26, 1 January 2024
Line 36:		Line 36:
	{{Nav VAX}}		{{Nav VAX}}

−	[[Category: Mainframe VAX ~~computers~~]]	+	[[Category: Mainframe VAX Computers]]
		+	[[Category: VAX Families]]

← Older revision		Revision as of 13:11, 6 December 2023
Line 36:		Line 36:
	{{Nav VAX}}		{{Nav VAX}}

−	[[Category: ~~VAXen]]~~	+	[[Category: Mainframe VAX computers]]
−	~~[[Category: DEC Mainframes~~]]

← Older revision		Revision as of 18:36, 13 August 2023
Line 37:		Line 37:

	[[Category: VAXen]]		[[Category: VAXen]]
		+	[[Category: DEC Mainframes]]

@@ Line 5: / Line 5: @@
 The VAX 9000 used the [[Extended Memory Interconnect|XMI]] as its [[input/output|I/O]] [[bus]]; up to 4 were possible in the largest systems. Models in the series included:
-* [[VAX 9000 Model 200 series]]
+* [[VAX 9000 Model 2x0]]
 ** [[VAX 9000 Model 210]]
-* [[VAX 9000 Model 400 series]]
+* [[VAX 9000 Model 4x0]]
 ** [[VAX 9000 Model 410]] - single-CPU
 ** [[VAX 9000 Model 420]] - double-CPU

@@ Line 19: / Line 19: @@
 ==Hardware==
 The CPU was built out of Multi-Chip Units (MCUs). Each CPU was implemented with 13 MCUs, with each MCU containing several ECL macrocell arrays, which contained the CPU [[logic]]. The gate arrays were fabricated in Motorola's "MOSAIC III" process, a [[bipolar]] process with a drawn width of 1.75 micrometres and three layers of interconnect. The MCUs were installed into a CPU planar module, which accommodated 16 MCUs and was 24 by 24 inches (610 mm) in size.
 {{semi-stub}}

@@ Line 26: / Line 26: @@
 * [http://www.bitsavers.org/pdf/dec/vax/9000/ VAX 9000] - documentation at [[Bitsavers]]
 ** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-9000S-SI-001_VAX_9000_System_Introduction_May90.pdf VAX 9000 Family System Introduction] (EK-9000S-SI-001)
 ** [http://www.bitsavers.org/pdf/dec/vax/9000/EK-KA90S-TD-001_VAX_9000_System_Technical_Description_May90.pdf VAX 9000 Family System Technical Description] (EK-KA90S-TD-001)