VAX Bus Interconnect - Revision history

Jnc: Fill out list of VAXBI options

2024-05-23T18:40:48Z

Fill out list of VAXBI options

2024-05-07T23:46:58Z

More accurate new category

2024-01-13T02:46:47Z

‎VAXBI cards: +DEBNT

2023-06-07T14:21:03Z

Bandwidth data added

2022-07-19T11:37:45Z

fix cat (after cat rename; have to move pages manually)

2022-07-17T09:42:55Z

Category added

2022-06-20T12:41:44Z

fixed typo

2022-06-09T15:26:52Z

‎External links: +bitsavers folder, etc

2022-06-08T11:34:09Z

Changed "Computer Interconnect" to "CI"

2022-06-05T15:59:30Z

@@ Line 11: / Line 11: @@
 The VAXBI had 52 signal lines in total; of these, a group of 32 lines are shared between [[address]] and data (like the earlier [[QBUS]]). [[Parity]] is used to protect both of these during transfer over the VAXBI.
 At the [[analog]] level, it is [[wired-OR]] (unlike its predecessor in the [[VAX-11/750]], the [[CPU/Memory Interconnect|CMI]], which was [[tri-state]]). [[Digital Equipment Corporation|DEC]] produced a custom [[integrated circuit|IC]] to interface to the VAXBI, implementing all the bus [[protocol]]s, leaving node designers free to concentrate on the design of their item.
-==VAXBI cards==
+==VAXBI bus adapters==
-* [[DEBNT]]
+* [[DB88 Adapter]] - adapter for the VAXBI to the [[NMI Memory Interconnect]] bus of the [[VAX 85xx, 87xx, and 88xx systems]]
 ==External links==

@@ Line 24: / Line 24: @@
 ** [http://www.bitsavers.org/pdf/dec/vax/vaxbi/EY-5554E-SG-0002_VAXBI_Adapters_Student_Guide_Feb87.pdf VAXBI Adapters Student Guide] (EY-5554E-SG-0002)
-[[Category: DEC Buses]]
+[[Category: VAX Buses]]
 [[Category: VAXBI]]

← Older revision		Revision as of 02:46, 13 January 2024
Line 12:		Line 12:

	At the [[analog]] level, it is [[wired-OR]] (unlike its predecessor in the [[VAX-11/750]], the [[CPU/Memory Interconnect\|CMI]], which was [[tri-state]]). [[Digital Equipment Corporation\|DEC]] produced a custom [[integrated circuit\|IC]] to interface to the VAXBI, implementing all the bus [[protocol]]s, leaving node designers free to concentrate on the design of their item.		At the [[analog]] level, it is [[wired-OR]] (unlike its predecessor in the [[VAX-11/750]], the [[CPU/Memory Interconnect\|CMI]], which was [[tri-state]]). [[Digital Equipment Corporation\|DEC]] produced a custom [[integrated circuit\|IC]] to interface to the VAXBI, implementing all the bus [[protocol]]s, leaving node designers free to concentrate on the design of their item.
		+
		+	==VAXBI cards==
		+
		+	* [[DEBNT]]

	==External links==		==External links==

@@ Line 7: / Line 7: @@
 The primary internal functions of the VAXBI are to do priority [[arbitration]] for use of the bus (fully distributed among all the nodes, with no 'master' node), and transfer data between the sub-systems, as well as carrying [[interrupt]]s. It is also used for a variety of lesser functions, such as initialization, etc. Some transactions on the VAXBI, such as interrupts, may be both single-responder and multi-responder.
-Data transfers can range from 1-16 bytes, in units of 1, 2 or 4 four-byte [[word]]s. The VAXBI is [[synchronous]] and [[clock]]ed (like the [[Synchronous Backplane Interconnect|SBI]] of the [[VAX-11/780]]). [[Cache]] operation is integrated into the operations on the VAXBI.
+Data transfers can range from 1-16 bytes, in units of 1, 2 or 4 four-byte [[word]]s. The VAXBI is [[synchronous]] and [[clock]]ed (like the [[Synchronous Backplane Interconnect|SBI]] of the [[VAX-11/780]]). [[Cache]] operation is integrated into the operations on the VAXBI. [[Bandwidth]] provided is 13.3 MB/sec.
 The VAXBI had 52 signal lines in total; of these, a group of 32 lines are shared between [[address]] and data (like the earlier [[QBUS]]). [[Parity]] is used to protect both of these during transfer over the VAXBI.

@@ Line 21: / Line 21: @@
 [[Category: DEC Buses]]
-[[Category: VAX Bus Interconnect]]
+[[Category: VAXBI]]
 [[Category: VAXen]]

← Older revision		Revision as of 09:42, 17 July 2022
Line 21:		Line 21:

	[[Category: DEC Buses]]		[[Category: DEC Buses]]
		+	[[Category: VAX Bus Interconnect]]
	[[Category: VAXen]]		[[Category: VAXen]]

@@ Line 1: / Line 1: @@
 The '''VAX Bus Interconnect''' (often given as '''VAXBI''') is the main [[bus]] in mid-range and high-end [[VAX]]en. In some machines, it connects all the main sub-systems, such as [[main memory]] and the [[Central Processing Unit|CPU]] (including [[multi-processor]]s); in the others, it is only used to support the [[input/output|I/O]] adapters and [[peripheral]]s.
-Machines which used it included the [[VAX 8200]] through the [[VAX 8800]]. For the 8200 and [[VAX 8300]] it performed all the functions listed above; for the others, it only supported the peripherals and I/O adapters. One of the latter was produced for the [[UNIBUS]]; peripherals included [[Ethernet]] and [[Computer Interconnect]|CI] interfaces.
+Machines which used it included the [[VAX 8200]] through the [[VAX 8800]]. For the 8200 and [[VAX 8300]] it performed all the functions listed above; for the others, it only supported the peripherals and I/O adapters. One of the latter was produced for the [[UNIBUS]]; peripherals included [[Ethernet]] and [[Computer Interconnect|CI]] interfaces.
 The VAXBI can hold up to 16 'nodes' (the formal term for VAXBI participating devices). No slot is specialized; any node can go into any slot.

@@ Line 16: / Line 16: @@
 * [http://www.bitsavers.org/pdf/dec/vax/handbook/VAX_Hardware_Handbook_Volume_2_1986.pdf VAX Hardware Handbook Volume 2] - the VAXBI is mentioned on page 1-5 (pg. 14 of the PDF) and 2-23&mdash;2-24 (pp. 46-47 of the PDF)
-* [http://www.bitsavers.org/pdf/dec/vax/vaxbi/EK-VBISY-RM-003_VAXBI_System_Reference_Manual_Feb89.pdf VAXBI System Reference Manual] (EK-VBISY-RM-003)
+* [http://www.bitsavers.org/pdf/dec/vax/vaxbi/ VAXBI] - documentation at Bitsavers
 [[Category: DEC Buses]]
 [[Category: VAXen]]

← Older revision	Revision as of 15:59, 5 June 2022
(No difference)