Difference between revisions of "DMA20 Memory Bus Adapter"
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| − | The '''DMA20 Memory Bus Adapter''' is an optional [[device controller|controller]] on [[KL10]] [[Central Processing Unit|CPUs]] which converts from the KL10's native SBus memory bus to an old-style [[PDP-10#Busses|PDP-10 memory bus]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory|core]] | + | The '''DMA20 Memory Bus Adapter''' is an optional [[device controller|controller]] on [[KL10]] [[Central Processing Unit|CPUs]] which converts from the KL10's native SBus [[main memory]] [[bus]] to an old-style [[PDP-10#Busses|PDP-10 memory bus]] (termed an 'KBus' here), to allow existing [[PDP-10]] [[core memory|core]] main memory to be used on one. (In a [[multi-processor]] system, each CPU has a separate DMA20, if configured to have one; the [[multi-port memory]] banks of [[PDP-10 memories]] will allow banks to be shared between CPUs.) |
==Implementation== | ==Implementation== | ||
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| + | [[Image:KBusQCLatched.jpg|250px|thumb|right|Memory bus Quick Latch connector (in latched position)]] | ||
The DMA20 is connected to the MBox of the KL10 via the SBus. Four separate KBuses are provided per CPU, to allow maximum (for the KL10) [[interleaving]]; the DMA20 can operate in 1-, 2- or 4-bus mode. | The DMA20 is connected to the MBox of the KL10 via the SBus. Four separate KBuses are provided per CPU, to allow maximum (for the KL10) [[interleaving]]; the DMA20 can operate in 1-, 2- or 4-bus mode. | ||
Revision as of 21:10, 12 October 2021
The DMA20 Memory Bus Adapter is an optional controller on KL10 CPUs which converts from the KL10's native SBus main memory bus to an old-style PDP-10 memory bus (termed an 'KBus' here), to allow existing PDP-10 core main memory to be used on one. (In a multi-processor system, each CPU has a separate DMA20, if configured to have one; the multi-port memory banks of PDP-10 memories will allow banks to be shared between CPUs.)
Implementation
The DMA20 is connected to the MBox of the KL10 via the SBus. Four separate KBuses are provided per CPU, to allow maximum (for the KL10) interleaving; the DMA20 can operate in 1-, 2- or 4-bus mode.
It consists of ten hex boards (an M8560, M8563, and eight M8558 modules) plugged into an I/O backplane (one shared with the DIA20 IBus Adapter) of the KL10; these are connected to memory bus connectors mounted lower down in that rack.
External links
- DMA20 Memory Bus Adapter Unit Description
- KL10-Based Physical Description - contains images of DMA20 backplanes and wiring, pp. 3-7-3-11; board configuration, pp. 3-27,3-28
