Difference between revisions of "DR11-L general-purpose interface"

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The '''DR11-L general-purpose interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, both input-only. It was a [[DEC card form factor|quad]] format card ('''M7864'''), and used an [[Small Peripheral Controller|SPC]] slot; it used [[programmed I/O]].
 
The '''DR11-L general-purpose interface''' was a [[UNIBUS]] [[device controller]] which provided a pair of 16-[[bit]] parallel ports, both input-only. It was a [[DEC card form factor|quad]] format card ('''M7864'''), and used an [[Small Peripheral Controller|SPC]] slot; it used [[programmed I/O]].
  
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Connection to the [[user]]'s device is via a pair of 40-[[pin]] [[Berg connector]]s; each is controlled by a separate set of [[register]]s (identical for the two connectors).
+
The DR11-L is roughly an input-only version of the earlier [[DR11-C general device interface]], but is not [[program compatible]] with the DR11-C.
 +
 
 +
Connection to the [[user]]'s device is via a pair of 40-[[pin]] [[Berg connector]]s; each is controlled by a separate set of [[register]]s (identical for the two connectors). Unlike the DR11-C, data coming in from the user's device is latched in the DR11-L, so may be read at leisure.
 +
 
 +
==Configuration==
 +
 
 +
The device's [[register]] and [[interrupt vector]] [[address]]es are set by a pair of [[Dual Inline Package|DIP]] switches. Unusually for a UNIBUS device, its [[interrupt]] priority is also set by the switches. Both the vector and priority may be read in the Control and Status Register.
  
−
The DR11-L is roughly an input-only version of the earlier [[DR11-C general device interface]], but is not [[program compatible]] with the DR11-C.
 
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<!--
 
 
==Registers==
 
==Registers==
  
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The device has three control and [[buffer]] [[register]]s, which can be configured to any three sequential [[word]] locations in the I/O page; the first DR11-C is normally configured to [[address]]es 767770-767774:
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The device has two pairs of control and [[buffer]] registers, which can be configured to any four sequential [[word]] locations in the I/O page; the first DR11-L is normally configured to addresses 764000-76406:
  
 
{| border=1
 
{| border=1
 
! Register !! Abbreviation !! Address
 
! Register !! Abbreviation !! Address
 
|-
 
|-
−
|Control and Status Register || DRCSR || 767770
+
|Control and Status Register A || DRCSRA || 764000
 +
|-
 +
|Data Buffer Register A || DBDBRA || 764002
 
|-
 
|-
−
|Output Buffer Register || DROUTBUF || 767772
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|Control and Status Register B || DRCSRB || 764004
 
|-
 
|-
−
|Input Buffer Register || DRINBUF || 767774
+
|Datia Buffer Register B || DBDBRB || 764006
 
|}
 
|}
  
 
In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.
 
In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics''.
  
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===Status Register (DRCSR)===
+
===Control and Status Register (DRCSR)===
 
{{16bit-header}}
 
{{16bit-header}}
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| ''REQ B'' || colspan=7 | Unused || ''REQ A'' || INT ENB A || INT ENB B || colspan=3 | Unused || CSR1 || CSR0
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| ''SI'' || colspan=6 | ''Vector'' || SO || ''RQ'' || RQE || colspan=2 | ''Prority'' || ''DR'' || ''CID'' || ''DL'' || DAE
 
{{16bit-bitout}}
 
{{16bit-bitout}}
  
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* REQ B - Request B - Signal from user's hardware which can be tested, or cause an [[interrupt]] (below)
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* SI - Status In: Signal from user's hardware which can be tested
−
* REQ A - Request A
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* SO - Status Out: Signal to user's hardware
−
* INT ENB A - Interrupt Enable A - When set, allows setting REQ A to cause an interrupt  
+
* RQ - Request: Signal from user's hardware which can be tested, or cause an interrupt  
−
* INT ENB B - Interrupt Enable B
+
* RQE - Request Enable: Allows setting RQ to cause an interrupt
−
* CSR1 - Signal to user's hardware (on connector 1)
+
* DR - Data Ready: Monitors the Data Ready In signal
−
* CSR0 - Signal to user's hardware (on connector 2)
+
* CID - CSR ID
 +
* DL - Data Latch: Set by Data Ready In to signal data has been latched
 +
* DAE - Data Accepted Enable: Enables Data Accepted Out to user's hardware
  
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===Input Buffer Register (INBUF)===
+
===Data Buffer Register (DRDBR)===
 
{{16bit-header}}
 
{{16bit-header}}
 
| colspan=16 | ''IN15 <-> IN0''
 
| colspan=16 | ''IN15 <-> IN0''
 
{{16bit-bitout}}
 
{{16bit-bitout}}
−
-->
 
  
 
[[Category:UNIBUS Peripherals]]
 
[[Category:UNIBUS Peripherals]]

Revision as of 04:37, 13 May 2020

DR11-L board

The DR11-L general-purpose interface was a UNIBUS device controller which provided a pair of 16-bit parallel ports, both input-only. It was a quad format card (M7864), and used an SPC slot; it used programmed I/O.

The DR11-L is roughly an input-only version of the earlier DR11-C general device interface, but is not program compatible with the DR11-C.

Connection to the user's device is via a pair of 40-pin Berg connectors; each is controlled by a separate set of registers (identical for the two connectors). Unlike the DR11-C, data coming in from the user's device is latched in the DR11-L, so may be read at leisure.

Configuration

The device's register and interrupt vector addresses are set by a pair of DIP switches. Unusually for a UNIBUS device, its interrupt priority is also set by the switches. Both the vector and priority may be read in the Control and Status Register.

Registers

The device has two pairs of control and buffer registers, which can be configured to any four sequential word locations in the I/O page; the first DR11-L is normally configured to addresses 764000-76406:

Register Abbreviation Address
Control and Status Register A DRCSRA 764000
Data Buffer Register A DBDBRA 764002
Control and Status Register B DRCSRB 764004
Datia Buffer Register B DBDBRB 764006

In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics.

Control and Status Register (DRCSR)

SI Vector SO RQ RQE Prority DR CID DL DAE
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • SI - Status In: Signal from user's hardware which can be tested
  • SO - Status Out: Signal to user's hardware
  • RQ - Request: Signal from user's hardware which can be tested, or cause an interrupt
  • RQE - Request Enable: Allows setting RQ to cause an interrupt
  • DR - Data Ready: Monitors the Data Ready In signal
  • CID - CSR ID
  • DL - Data Latch: Set by Data Ready In to signal data has been latched
  • DAE - Data Accepted Enable: Enables Data Accepted Out to user's hardware

Data Buffer Register (DRDBR)

IN15 <-> IN0
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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