Difference between revisions of "F-11 chip set"

From Computer History Wiki
Jump to: navigation, search
(move content to kef11-A page)
m (typo)
Line 3: Line 3:
 
The main CPU was implemented in two chips (carried on a single DIP carrier): the data paths chip (DC302, DEC part # 21-15541-Ax, where x is a capital letter giving the revision; B is the most common, although C has been seen), which contains the registers, ALU, etc; and the control chip (DC303, DEC part # 23-001C7-Ax, although only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic.
 
The main CPU was implemented in two chips (carried on a single DIP carrier): the data paths chip (DC302, DEC part # 21-15541-Ax, where x is a capital letter giving the revision; B is the most common, although C has been seen), which contains the registers, ALU, etc; and the control chip (DC303, DEC part # 23-001C7-Ax, although only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic.
  
Unlike the first microprocessor implementation (the [[LSI-11]]), the F-11 chip set implemented the full [[PDP-11 architecture]], including the optional [[KTJ11-A memory management chip]] which implemented standard [[PDP-11 Memory Management]], and the optional [[KEF11-A floating point chip]] which implemented the [[FP11 floating point|FP11]]-compatible f[[floating point]].
+
Unlike the first microprocessor implementation (the [[LSI-11]]), the F-11 chip set implemented the full [[PDP-11 architecture]], including the optional [[KTJ11-A memory management chip]] which implemented standard [[PDP-11 Memory Management]], and the optional [[KEF11-A floating point chip]] which implemented the [[FP11 floating point|FP11]]-compatible [[floating point]].
  
 
(The KEF11-A requires the KTJ11-A, since the floating point registers are actually in the KTJ11-A; probably because the KEF11-A is microcode, and there aren't enough pins for both the data bus, and the microcode bus.) There is also a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS).
 
(The KEF11-A requires the KTJ11-A, since the floating point registers are actually in the KTJ11-A; probably because the KEF11-A is microcode, and there aren't enough pins for both the data bus, and the microcode bus.) There is also a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS).

Revision as of 01:18, 15 November 2016

The F-11 chip set (code-named 'Fonz') was DEC's second microprocessor implementation of the PDP-11 architecture. It was used in the KDF11 CPUs.

The main CPU was implemented in two chips (carried on a single DIP carrier): the data paths chip (DC302, DEC part # 21-15541-Ax, where x is a capital letter giving the revision; B is the most common, although C has been seen), which contains the registers, ALU, etc; and the control chip (DC303, DEC part # 23-001C7-Ax, although only the A revision has been seen), which contains microcode and a small amount of miscellaneous logic.

Unlike the first microprocessor implementation (the LSI-11), the F-11 chip set implemented the full PDP-11 architecture, including the optional KTJ11-A memory management chip which implemented standard PDP-11 Memory Management, and the optional KEF11-A floating point chip which implemented the FP11-compatible floating point.

(The KEF11-A requires the KTJ11-A, since the floating point registers are actually in the KTJ11-A; probably because the KEF11-A is microcode, and there aren't enough pins for both the data bus, and the microcode bus.) There is also a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS).

The KTJ11-A chip was the DC304, DEC part # 21-15542-0n (where n is a digit giving the revision; 0 and 1 have been seen).

External links