Difference between revisions of "J-11 chip set"

From Computer History Wiki
Jump to: navigation, search
(+link to J11 page)
m (avoid dab, clarify)
Line 3: Line 3:
 
The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package|DIP]] carrier.
 
The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package|DIP]] carrier.
  
It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11]] [[floating point]] support (using [[microcode]]), it can operate with an [[FPJ11]] floating point accelerator chip.
+
It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11 floating point|FP11]] [[floating point]] support (using [[microcode]]), it can operate with an [[FPJ11]] floating point accelerator chip for higher performance.
  
 
Most uses on DEC PDP-11 [[Central Processing Unit|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].
 
Most uses on DEC PDP-11 [[Central Processing Unit|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].

Revision as of 14:06, 17 September 2019

J-11

The J-11 (formally, the DCJ11, although DEC documentation uses both names) is a high-performance CMOS implementation of the PDP-11 architecture, used in both the KDJ11 CPUs, and a variety of peripherals. It was implemented in two chips ('Control' and 'Data') carried on a single 60-pin DIP carrier.

It implements the full PDP-11 Memory Management architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in FP11 floating point support (using microcode), it can operate with an FPJ11 floating point accelerator chip for higher performance.

Most uses on DEC PDP-11 CPU boards (all for the QBUS) contain an external cache.

External link