Difference between revisions of "KA11 changes for the KT11-B"

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(→‎KA11 modifications: added flip chip)
(→‎Wires removed: add table)
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An M138 FLIP CHIP (octal three-input NAND gates) is also plugged into the KA11 backplane (in slot B08, otherwise unused), to provide additional gates.
 
An M138 FLIP CHIP (octal three-input NAND gates) is also plugged into the KA11 backplane (in slot B08, otherwise unused), to provide additional gates.
 +
 +
===Wires removed===
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{| class="wikitable"
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! From !! To !! Signal !! Colour
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|-
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| B02T2 || F08U2 || MSYN || rowspan="6" style="text-align:center;" | Orange
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|-
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| D12C2 || D12S1 || GND 12
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|-
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| E04K1 || E07P2 || CLKT
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|-
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| E03F1 || E04L1 || SCLK
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|-
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| D11B1 || C06J1 || ODD ADRS ERR
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|-
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| C06J1 || D02N1 || ODD ADRS ERR
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|-
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| D12S1 || D12T1 || GND 12 || Brown
 +
|}

Revision as of 02:37, 22 August 2016

The KT11-B Paging Option for the PDP-11/20 involves some modifications to the KA11 CPU. Those changes are documented in a DEC print set, 7605961-0, "Central Processor for KT11-B".

Alas, there's only one known set of these prints for the KT11-B changes to the KA11 - and that set is missing a page: "PC Board Modifications", D-AP-7605961-0-10.

Luckily, there is probably just duplicate information elsewhere (including a hand-modified set of KA11 prints, showing the changes to suppport the KT11-B) to allow it to be reproduced.

Print set

The following prints are included in the "Central Processor for KT11-B" set:

Drawing Sheets Title
D-CS-7605961-0-3 3 State Control - M727 K2
D-CS-7605961-0-4 3 Priority - M824 K3
D-CS-7605961-0-5 5 Bus Interface & Instruction Register - M725 K9
D-CS-7605961-0-6 4 Instruction Register Decode - M726 K10
D-CS-7605961-0-7 3 Flag Control - M822 K12
D-CS-7605961-0-8 4 Bus & Console Control - M724 K13

KA/KT Interface

The KA11 and KT11-B are connected by a single cable which carries specific signals, as well as the UNIBUS. On the KT11 end, it plugs into slot D12, and on the KA11 end, into slot B09. The cable pinout is:

Pin Source Signal  ! Pin Source Signal
A1 - Ground A2  ? xx
B1 KA11 Odd address error B2  ? xx
C1 - Ground C2 - Ground
D1 KT11 PGC 04 D2 KA11 RTS
E1 KA11 DEST E2 KA11 CLKT
F1 - Ground F2 - Ground
H1 KA11 SOURCE H2 KA11 -TRAPS
J1 KA11 ISR 12 J2 - Ground
K1 - Ground K2 KA11 SERVICE
L1 KA11 ISR 7 L2 - Ground
M1 KA11 -RTI M2 KA11 TIME OUT
N1 - Ground N2 - Ground
P1 KA11 JSR P2 KA11 FETCH
R1 - Ground R2 - Ground
S1 KT11 CLK NPR S2 KA11 TRAP
T1 - Ground T2 KA11 [ST+SR] K13-3
U1  ? xx U2 - Ground
V1  ? xx V2 KT11 Force timeout

(Signals partially in lower case are not formal names from the prints, but give a sense of what the signal does.)

KA11 modifications

An M138 FLIP CHIP (octal three-input NAND gates) is also plugged into the KA11 backplane (in slot B08, otherwise unused), to provide additional gates.

Wires removed

From To Signal Colour
B02T2 F08U2 MSYN Orange
D12C2 D12S1 GND 12
E04K1 E07P2 CLKT
E03F1 E04L1 SCLK
D11B1 C06J1 ODD ADRS ERR
C06J1 D02N1 ODD ADRS ERR
D12S1 D12T1 GND 12 Brown
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