Difference between revisions of "KD11-A CPU"
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Other CPU options included the [[KJ11-A Stack Limit Register]], and the [[KW11-L Line Time Clock]] (the latter being a standard option across a number of PDP-11 CPUs). | Other CPU options included the [[KJ11-A Stack Limit Register]], and the [[KW11-L Line Time Clock]] (the latter being a standard option across a number of PDP-11 CPUs). | ||
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Revision as of 16:00, 17 February 2018
The KD11-A PDP-11 CPU for the PDP-11/35 and PDP-11/40 was a multi-board micro-programmed processor contained on four hex cards, and one quad card.
Support for the EIS was optional, with the KE11-E Extended Instruction Set, a hex card. There was also optional floating point hardware, the KE11-F Floating Instruction Set, a quad card; it was not the full FP11 Floating Point, but the minimal FIS floating point.
Memory management support was also optional, with the KT11-D Memory Management, another hex card; it too was not the full PDP-11 Memory Management, but the simplified subset.
Other CPU options included the KJ11-A Stack Limit Register, and the KW11-L Line Time Clock (the latter being a standard option across a number of PDP-11 CPUs).
