Difference between revisions of "KD11-A CPU"

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The '''KD11-A''' [[PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/35]] and [[PDP-11/40]] was a multi-board [[micro-programming|micro-programmed]] processor contained on four [[DEC card form factor|hex]] cards, and one quad card.
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The '''KD11-A''' [[PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/35]] and [[PDP-11/40]] was a multi-board [[microcode|micro-programmed]] processor.
  
 
Support for the [[PDP-11 Extended Instruction Set|EIS]] was optional, with the [[KE11-E Extended Instruction Set]], a hex card. There was also optional [[floating point]] hardware, the [[KE11-F Floating Instruction Set]], a quad card; it was not the full [[FP11 Floating Point]], but the minimal [[FIS floating point]].
 
Support for the [[PDP-11 Extended Instruction Set|EIS]] was optional, with the [[KE11-E Extended Instruction Set]], a hex card. There was also optional [[floating point]] hardware, the [[KE11-F Floating Instruction Set]], a quad card; it was not the full [[FP11 Floating Point]], but the minimal [[FIS floating point]].
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Other CPU options included the [[KJ11-A Stack Limit Register]], and the [[KW11-L Line Time Clock]] (the latter being a standard option across a number of PDP-11 CPUs).
 
Other CPU options included the [[KJ11-A Stack Limit Register]], and the [[KW11-L Line Time Clock]] (the latter being a standard option across a number of PDP-11 CPUs).
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==Implementation==
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The basic KD11-A was contained on four [[DEC card form factor|hex]] cards:
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* M7231 - Data Paths
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* M7233 - IR Decode
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* M7234 - Timing
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* M7235 - Status
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and one quad card:
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* M7232 - μword
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all of which plugged into a [[wire-wrap]]ped custom [[backplane]] dual [[system unit]].
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The KE11-E Extended Instruction Set, KE11-F Floating Instruction Set, and KT11-D Memory Management option cards all plugged into pre-wired slots in this backplane, as did the KJ11-A Stack Limit Register and the KW11-L Line Time Clock.
  
 
[[Category:PDP-11 Processors]]
 
[[Category:PDP-11 Processors]]
 
[[Category:UNIBUS Processors]]
 
[[Category:UNIBUS Processors]]

Revision as of 01:17, 21 January 2019

The KD11-A PDP-11 CPU for the PDP-11/35 and PDP-11/40 was a multi-board micro-programmed processor.

Support for the EIS was optional, with the KE11-E Extended Instruction Set, a hex card. There was also optional floating point hardware, the KE11-F Floating Instruction Set, a quad card; it was not the full FP11 Floating Point, but the minimal FIS floating point.

Memory management support was also optional, with the KT11-D Memory Management, another hex card; it too was not the full PDP-11 Memory Management, but the simplified subset.

Other CPU options included the KJ11-A Stack Limit Register, and the KW11-L Line Time Clock (the latter being a standard option across a number of PDP-11 CPUs).

Implementation

The basic KD11-A was contained on four hex cards:

  • M7231 - Data Paths
  • M7233 - IR Decode
  • M7234 - Timing
  • M7235 - Status

and one quad card:

  • M7232 - μword

all of which plugged into a wire-wrapped custom backplane dual system unit.

The KE11-E Extended Instruction Set, KE11-F Floating Instruction Set, and KT11-D Memory Management option cards all plugged into pre-wired slots in this backplane, as did the KJ11-A Stack Limit Register and the KW11-L Line Time Clock.